Samsung Electronics Co., Ltd.

Hoyoung Song

Sangwoong Shin

Yanggyoon Loh

Sungchul Park

Sunghye Cho

Myungkyu Lee

Sanguhn Cha

Chankyung Kim

Soo-Ho Cha

Kwangchol Choe

Hyunki Kim

Jong-Min Oh

Dongha Kim

Donghyun Sohn

Chiwook Kim

Yung-young Lee

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

Semiconductor memory devices and memory systems

A memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.

Memory device performing refresh operation based on a random value and method of operating the same

A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.

Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof

A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

Memory device including memory cell for generating reference voltage

Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.

Post package repairing method, method of preventing multiple activation of spare word lines, and semiconductor memory device including fuse programming circuit

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Hwaseong-si, South Korea

Hoyoung Song