Samsung Electronics Co., Ltd.

Hoyoun Kim

Kijun Lee

Myungkyu Lee

Jungmin You

Seongjin Cho

Wonhyung Song

Hijung Kim

Suhun Lim

Jongmin Lee

Sunghye Cho

Sungrae Kim

Chanki Kim

Eunchul Kwon

A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

Method of controlling row hammer and a memory device

A memory controller includes an error correction code (ECC) circuit configured to receive a data burst and generate first ECC data or second ECC data, and a processor configured to control operations of the ECC circuit. The ECC circuit includes an ECC select circuit configured to select and output one of first ECC conversion data and second ECC conversion data, based on an ECC select signal from outside the memory controller, and an ECC conversion circuit configured to generate the first ECC data by encoding the data burst, based on the first ECC conversion data, or generate the second ECC data by encoding the data burst, based on the second ECC conversion data. The second ECC conversion data is set to be capable of correcting an error generated in one or more preset protected bits among bits included in each of pieces of partial data included in the data burst.

Memory controller and memory system including the same

A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

Memory device, memory system having the same and operating method thereof

A refresh control circuit includes: a counting bloom filter that includes N hash control logics, each of which performs a hash operation on input data and outputs an M-bit sequence and M counters, each of which corresponds to a bit of the M-bit sequence, and updates count values of corresponding counters indicated by values of the M-bit sequences obtained from the N hash logics by using an address of a row of the memory cells as the input data; a candidate row determiner that determines rows of the memory cells accessed in a predetermined period in which the count values of the corresponding counters are greater than a threshold value as candidate rows for a target refresh operation; and a target refresh controller that outputs target refresh signals for rows of the candidate rows adjacent to one or more target rows determined by the candidate row determiner.

Memory system, refresh control circuit, and refresh control method

A memory controller, to control a semiconductor memory device, includes an access pattern profiler, a row hammer prediction neural network, and a memory interface. The access pattern profiler generates an access pattern profile based on a row access pattern on a portion of memory cell rows of the semiconductor memory device during a reference time interval posterior to a refresh interval during which the memory cell rows are refreshed. The row hammer prediction neural network predicts a probability of occurrence based on the access pattern profile. In response to the probability being equal to or greater than a reference value, the row hammer prediction neural network generates a hammer address, an alert signal indicating that the row hammer occurs, and an outcast row list. The memory interface transmits the hammer address, the outcast row list, and the alert signal to the semiconductor memory device.

A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

Memory controllers, memory systems, and memory modules

A memory system is provided. The memory system includes at least one memory device, and a controller configured to control the at least one memory device, wherein the controller includes: an error correction circuit configured to correct an error in data read from the at least one memory device, a codeword error counter configured to obtain a syndrome of a current codeword error based on a codeword error occurring in the error correction circuit, and to obtain a weighted codeword error count value by comparing the obtained syndrome with a previous syndrome, and an alert device configured to generate a warning signal for preventing an uncorrectable error of the at least one memory device according to the weighted codeword error count value.

Controller for preventing uncorrectable error in memory device, memory device having the same, and operating method thereof

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.

Semiconductor memory devices and methods of operating semiconductor memory devices

A memory controller to control a memory module includes an error correction code (ECC) engine, a central processing unit to control the ECC engine and an error managing circuit. The ECC engine performs an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome in a read operation, corrects correctable error in a user data set based on the first syndrome and the second syndrome and provides the error management circuit with the second syndrome associated with the correctable error. The error managing circuit counts error addresses associated with correctable errors detected through read operations, stores second syndromes associated with the correctable errors by accumulating the second syndromes, determines attribute of the correctable errors based on the counting and the accumulated second syndromes, and determine an error management policy on a memory region associated with the correctable errors.

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Seoul, South Korea

Hoyoun Kim