Oracle International Corporation

Oracle America, Inc.

Hoyeol Cho

Ioannis Orginos

Jinho Kwack

Heechoul Park

Jungyong Lee

Pangjie Xu

Song C Kim

Kanghoon Jeon

Daniel Fung

Myung Gyoo Won

Joann Lam

Peter Normand Labrecque

Singrong Li

Claire Ni

Jilong Shan

Jason T Su

Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Memory bitcell with column select

Systems, methods, and other embodiments associated with using a local voltage regulator embedded within a memory sub-array are described. In one embodiment, a memory device includes a memory sub-array including a set of memory cells and a local voltage regulator. The local voltage regulator is configured to generate a local voltage for powering the memory sub-array. The memory device includes switch logic connected to the memory sub-array and configured to select between the local voltage and a source voltage to power the memory sub-array. The source voltage is provided to the memory device by a host device.

Memory power selection using local voltage regulators

Embodiments include systems and methods for improving power consumption characteristics of reverse directories in microprocessors. Some embodiments operate in context of multiprocessor semiconductors having cache hierarchies in which multiple higher-level caches share lower-level caches. Lower-level cache is coupled with reverse directories associated with respective ones of the higher-level caches. Each reverse directory can be segregated into two reverse sub-directories, one reverse sub-directory for relatively high-frequency accesses (e.g., updating 'valid' and/or 'private' information), and the other reverse sub-directories for relatively low-frequency accesses updating &#x201c;index&#x201d; and &#x201c;way&#x201d; information). During a write mode operation, when the reverse directories are updated, the write operation is performed only on the sub-directories having the entries invoked by the update, such that write operations can frequently consume only a fraction (e.g., halt) of the power of a conventional reverse directory write operation.

Power saving for reverse directory

Systems, methods, and other embodiments associated with conserving power using variable width pulses to activate word lines are described. In one embodiment, a memory device embedded within a processor. The memory device includes a pulse shaper to generate a first timing delay and a second timing delay according to power state information. The power state information indicates a current operating state of the processor. The memory device includes a memory controller to generate, in response to receiving a request to access one or more memory cells of the memory device, a word line enable signal that activates the one or more memory cells according to the first timing delay, the second timing delay, and a clock signal by generating the word line enable signal with a pulse width that is variable to conserve power when the state information indicates the processor is in a power saving state.

Variable pulse widths for word line activation using power state information

Embodiments provide centralized redundancy block repair for memory circuits. Certain embodiments are implemented in context of high-performance memory, such as last-level cache design, where the primary memory bank often uses high-density memory cells ('bitcells') and supports long self-bitline structures to increase compactness. In such contexts, it can be difficult to finish read operations within a single cycle, even when the entire cache is divided into small bank pieces. Bank-interleaved structure in clusters can be implemented to allow access to different memory banks in consecutive cycles, thereby achieving overall single circle throughput (i.e., the latency can be masked by the interleaving). Accordingly, some embodiments of the centralized block repair can support bank interleaved access, for example, with a strict single-cycle throughput. Some embodiments can also support other features, such as row repair and/or column repair.

Centralized memory repair block

Systems, methods, and other embodiments associated with improving a static noise margin of memory cells by using charge sharing to under-drive a wordline are described. In one embodiment, a system includes power logic to, in response to a memory request, connect a voltage source with a virtual power network to store an electric charge within the virtual power network based on a voltage from the voltage source. The virtual power network includes a network of interconnects that electrically connect a plurality of driver interconnects. The system includes wordline logic to under-drive a requested wordline of a plurality of wordlines by connecting the requested wordline with the virtual power network to share the electric charge stored in the virtual power network with the requested wordline. The wordline logic under-drives a voltage of the requested wordline to be lower than a source voltage provided by the voltage source.

Wordline under-driving using a virtual power network

Systems, methods, and other embodiments associated with speculating whether a read request will cause an access to a memory are described. In one embodiment, a method includes detecting, in a memory, a read request from a processor and speculating whether the read request will cause an access to a memory bank in the memory based, at least in part, on an address identified by the read request. The method selectively enables power to the memory bank in the memory based, at least in part, on speculating whether the read request will cause an access to the memory bank.

Speculation to selectively enable power in a memory

A memory array for process variation tolerant bypass operation. The memory array may utilize normal read operation data path of a memory I/O module. Accordingly, the speed at which the bypass operation may be executed may be increased. Furthermore, a potential for false read operations introduced by the utilization of the normal read operation data path of the memory I/O module may be reduced using a protect mechanism operable to block the output of false reads from the memory array.

High speed read access memory array with variation tolerant bypass scheme with protection circuit

Systems, methods, and other embodiments associated with bit line equalization are described. Systems and methods described herein provide secondary bit line equalization for embedded memory systems to reduce equalization time and improve memory performance. The reduction in equalization time is accomplished by adding a secondary equalizer in addition to a standard primary equalizer for a column of memory cells.

Secondary bit line equalizer

Systems and methods are described herein that reduce the read latency of a cache by separating read and write column select signals that cause the cache to initiate certain read and write operations, respectively.

Separate read/write column select control

Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively coupling the memory cell bus to a first power plane and a second power plane, where the memory cell bus is coupled to the second power plane when the power circuit is substantially off, and a bit line pre-charge circuit coupled to the power circuit, where the power circuit selectively couples the first power plane to the pre-charge circuit for a predetermined period of time.

Methods and apparatuses for improving reduced power operations in embedded memory arrays

A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM.

Dynamically controlled voltage regulator for a memory

A method and system that can be used with signals read from a memory cell or other feature that varies in amplitude as a function of the data being read. The data read from the memory cell may be of the type that decreases in voltage when a 'low' is being read and that remains at a predetermined voltage when a 'high' is being read. The method and system may vary a reference to voltage used to judge whether the data is being read &#x2018;low&#x2019; or &#x2018;high&#x2019;.

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Palo Alto, CA, United States of America

Hoyeol Cho