Nvidia Corporation

Howard Tsai

Paul Gyugyi

Dmitry Vyshetsky

Neal Meininger

Nirmal Raj Saxena

Benjamin K Dodge

Tony Yuhsiang Cheng

Hon Fei Chong

Tsungyi Lin

Dmitry Vyshetski

Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device.

Virtualization of chip enables

A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.

Memory controller adaptable to multiple memory devices

A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.

Method and system for improved flash controller commands selection

A system for improving direct memory access (DMA) offload. The system includes a processor, a data DMA engine and memory components. The processor selects an executable command comprising subcommands. The DDMA engine executes DMA operations related to a subcommand to perform memory transfer operations. The memory components store the plurality of subcommands and status data resulting from DMA operations. Each of the memory components has a corresponding token associated therewith. Possession of a token allocates its associated memory component to the processor or the DDMA engine possessing the token, making it inaccessible to the other. A first memory component and a second memory component of the plurality of memory components are used by the processor and the DDMA engine respectively and simultaneously. Tokens, e.g., the first and/or the second, are exchanged between the DDMA engine and the processor when the DDMA engine and/or the microcontroller complete accessing associated memory components.

Method and system for improving direct memory access offload

An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.

Method and system for fast two bit error correction

A computing system has a mode of operation in which at least two different memory parameter profiles are read by a BIOS to configure memory. In one implementation the memory parameter profiles are stored in a serial presence detect memory using an extended serial presence detect format.

Growing community of inventors

Cupertino, CA, United States of America

Howard Tsai