International Business Machines Corporation

Howard Thomas Olnowich

James William Feeney

Robert Francis Lusch

John David Jabusch

Jehoshua Bruck

Michael Hans Fisher

Arthur Robert Williams

Michael Anthony Maniguet

George William Wilhelm, Jr

Thomas Norman Barker

Michael W Dotson

Eli Upfal

Joel M Gould

Peter Anthony Franaszek

Philip Lee Childs

Peter Michael Kogge

Joseph Francis Skovira

Philip Heidelberger

Christos J Georgiou

Joseph M Mosley

Christopher S Murray

William Russell Belknap

Stephen Gouze Luning

Miguel M Blaum

Eliezer Upfal

Ashok Raj Saxena

Buddy F Stansbury

Donald George Grice

Bharat D Rathi

Robert Betts

Marc Snir

James W Eldridge

Gilbert C Vandling

Larry William Fitchett

David Brian Kirk

Karl David Schubert

Anujan Mangala Varma

Omar A Saiyid

Louise Irene Cleary

Gilbert Clyde Vandling, Iii

Erwin R Berger

Buddy Floyd Stansbury

A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.

Memory controller for controlling memory accesses across networks in distributed shared memory processing systems

A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.

Multi-tasking adapter for parallel network applications

A network adapter capable of adapting its transmission speed to that of another adapter of the same or slower speed so as to mix adapters of different speeds in the same communication network. In send mode, the adapter selects one of a plurality of transmission speeds based on the message header including a field specifying the message speed, which speed is known to be supported by the adapter at the addressed receive node. The sending adapter prefixes the message with a synchronization byte which defines transmission speed selected and transmits the message at the selected speed. In receive mode, the adapter decodes within one clock cycle the message speed from the message synchronization byte, and responsive thereto generates the clock for gating the receive message into adapter memory.

Networks adapters for multi-speed transmissions

Cache coherent network adapter for scalable shared memory processing systems

An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

Apparatus for coupling a bus-based architecture to a switch network

Contention losses are minimized in path searching, circuit-switched networks by adding intelligence to the last stage of the network. A count of number of bytes remaining to be transferred in each active message is maintained in real time for each output port of the network. If contention arises at the last stage switch being requested in camp-on mode to make a connection to a busy output port, the switch checks the bytes remaining count and responds differently depending on how the bytes remaining count compares to a preset threshold register. If the count remaining is below the threshold, the last stage switch accepts the camp-on request, because the desired output port will be available shortly. If the count remaining is above the threshold or below the threshold but another user is camped-on, the switch rejects the camp-on request to the last stage, because the desired output port will not be available shortly. In this case further path searching would be meaningless. A different message to a different destination (output port) is tried, and later the contended message is retried.

Method and apparatus for minimizing contention losses in networks

Disclosed is is a switch-based network interconnection which uses intelligent switching apparatus devices for improving the performance and connection establishing capability of multi-stage switching networks. The invention method is particularly effective In asynchronous circuit-switched networks. The most important feature of the invention methodology is the an increasing probability for the success of making a connection through all the stages of a multi-satge network. As a connection progresses through a multi-stage network, it must win successive stages of the network, one at a time, until it has made its way from on side of the network to the other and established the commanded source-to-destination connection. The uniqueness in the present invention is that as the connection at each stage of the network is established, looking forward to the next stage, the probability will be greater of establishing the next connection without encountering blocking than it was for the present stage. This presents an ever increasing probability for establishing a successful connection as a path works its way through the network. This is opposite of most traditional networks, whose probabiltiy for success diminishes with every stage in the connection sequence.

Increasing probability multi-stage network

A new asynchronous approach used to quickly and dynamically switch input port connections to output port connections and to resolve contention. The switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays&mdash;on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.

All-node switch-an unclocked, unbuffered, asynchronous switching apparatus

Bi-directional network adapter for interfacing local node of shared

Memory controller for controlling memory accesses across networks in

A dynamic allocation system and method is provided for allocating memory bandwidth associated with a store and forward memory communicating between a node processsor and a network. Dynamic allocation is controlled by a state machine in a network adapter, which monitors on a real time basis the active users of the network adapter memory, the node processor writing or reading adapter memory, the network sending port, and the network receiving port. Bandwidths are allocated to users with instant response to user bandwidth demand changes. Programmable options allow a node processor to control bandwidth allocations for various user scenarios.

Method and apparatus for dynamic allocation of bandwidth to/from network

Cache coherent network adapter for scalable shared memory processing

Network adapters for multi-speed transmissions

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Endwell, NY, United States of America

Howard Thomas Olnowich