Microsemi Solutions (us), Inc.

Pmc-sierra Us, Inc.

Microsemi Storage Solutions (u.s.), Inc.

Howard Shih Hao Chang

Kenneth Wagner

Kanwaldeep Singh Chhokar

Yoo Ho Cho

Redentor De La Merced

A method and system of merging one-bit cells in an integrated circuit layout, comprising a database to store the layout, a placer in communication with the database to update the layout, and a merger in communication with the placer. The merger is configured to: identify a set of one-bit cells in the integrated circuit layout; determine a set of merge cells, from among the identified set of one-bit cells, to be merged into a multi-bit register, the determination of the set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the set of merge cells, and each merge cell sharing a clock with the other merge cells in the set of merge cells; and generate instructions to the placer for merging the set of merge cells to form the multi-bit register in the integrated circuit layout.

Method and system of merging memory cells into multi-bit registers in an integrated circuit layout

A voltage detector to detect the voltage level of a switched power supply associated with a power gated region of an integrated circuit. The voltage detection circuit, which can be described as a modified Schmitt trigger circuit, comprises PMOS and NMOS transistors, and an added stack of NMOS transistors to set the output to a value of 1 in response to detection of an input voltage at the input greater than an operational voltage of the switched power supply, for example approximately 80% VDD and above. A pull-down circuit actively pulls the circuit output low before the circuit input drops below the low input threshold. Optional additional NMOS transistors provide the capability to adjust the threshold. The voltage detector circuit can be calibrated and used to detect whether or not the switched power supply associated with a power gated design has reached its operational voltage level.

Apparatus for voltage detection in an integrated circuit

The present disclosure provides a monitoring system for monitoring the operation of an integrated circuit, the monitoring system comprising: a reference circuit comprising a reference signal delay path and an output for outputting a reference signal; a monitoring circuit, the monitoring circuit comprising: a programmable delay line for providing a controllably selectable delay path; and an output for outputting a delayed signal; a comparison circuit, for comparing the reference signal to the delayed signal and determining whether the error has occurred based on the comparison.

Circuit and method for real-time monitoring of process, temperature, and voltage variations

A duty-cycle distortion self-correcting delay line has an even number of programmable delay lines connected in series between a data signal input and a data signal output. Each programmable delay line is paired with a corresponding inverting element. A data signal propagated from the input to the output is passed un-inverted in half of the delay lines and is passed inverted in the other half of the delay lines. When the data signal is a square wave clock signal, a duty cycle distortion caused by the delay lines passing the un-inverted signal is cancelled by a duty cycle distortion caused by the delay lines passing the inverted signal. The inverting elements may be XNOR or XOR gates connected to an anti-aging signal input which, when asserted, maintains all of the delay lines in order to avoid differential aging effects leading to acquired duty cycle distortion.

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Vancouver, Canada

Howard Shih Hao Chang