Texas Instruments Corporation

Howard Raeburn Test

Donald Charles Abbott

Willmar E Subido

Gonzalo Amador

Wei-Yan Shih

Michael A Lamson

George A Bednarz

Homer B Klonis

Reginald W Smith

Albert H Kuckhahn

Michael R Vinson

Gretchen W Roeding

Placement of an encapsulation material adhesion promoter onto a semiconductor device leadframe can be performed through the use of an offset printing apparatus such as a rotogravure printing apparatus or a tampoprint printing apparatus. This can provide accurate and low-cost placement of the adhesion promoter.

Offset gravure printing process for improved mold compound and die attach adhesive adhesion on leadframe surface using selective adhesion promoter

A metal structure for a contact pad of a wafer or substrate (), which have copper interconnecting traces () surrounded by a barrier metal layer (). The wafer or substrate is protected by an insulating overcoat (). In the structure, the barrier metal layer is selectively exposed by a window () in the insulating overcoat. A layer of copper (), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel () is adherent to the copper layer and a layer of noble metal () is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Structure and method for bond pads of copper-metallized integrated circuits

A metal structure () for a contact pad of a semiconductor, which has interconnecting traces of a first copper layer (). The substrate is protected by an insulating overcoat (). The first copper layer of first thickness and first crystallite size is selectively exposed by a window () in the insulating overcoat. A second copper layer () of second thickness covers conformably the exposed first copper layer. The second layer is deposited by an electroless process and consists of a transition zone, adjoining the first layer and having copper crystallites of a second size, and a main zone having crystallites of the first size. The distance a void can migrate from the second layer is smaller than the combined thicknesses of the first and second layers. A nickel layer () is on the second copper layer, and a noble metal layer () is on the nickel layer.

Copper-metallized integrated circuits having electroless thick copper bond pads

The present invention provides a metallization scheme, a method for manufacturing the metallization scheme, and an integrated circuit including the metallization scheme. In one aspect, the metallization scheme () includes a protective layer () located over a substrate (), and a conductive layer () located over the protective layer (). The metallization scheme () further includes a stress-reducing low-modulus material () located between the protective layer () and the conductive layer ().

Metallization scheme including a low modulus structure

A semiconductor device has a semiconductor chip with a periphery and an IC organized in a core portion and a peripheral portion. The IC has a top level of interconnecting metal traces () from the peripheral portion to the core portion; the traces are covered by an insulating overcoat () which has peripheral windows to expose bond pads. The circuit further has at least one level of metal lines () on top of the insulating overcoat; the lines lead from the chip periphery towards the chip core, wherein each line () is substantially parallel to one of the traces () underneath the insulating overcoat and vertically aligned therewith. After assembling the chip onto a leadframe with segments (), bonding wires () connect the bond pads () and the metal lines () with the segments.

Wire bonded semiconductor device having low inductance and noise

An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In accordance with the present invention the nickel bath is placed and remains in hydrogen saturation by providing a piece of metal that remains in the nickel plating tank before and during the plating process.

Method to achieve continuous hydrogen saturation in sparingly used electroless nickel plating process

Wire bonding process for copper-metallized integrated circuits

A flexible plating method by continuously controlling the hydrogen concentration of the plating bath by adding controlled amounts of hydrogen gas. The control of the hydrogen concentration is provided by selected distribution and number of nozzles and size of orifices; and predetermined pressure and duration of hydrogen gas flowing through the nozzles, wherein pressure and duration may be variable with time. The control of the hydrogen concentration is selected to provide a ramp-up phase, needed for a rapid plating start, followed by a saturation phase, for consistent plating stability. With metal layer plating under control, a robust, reliable and low-cost metal structure enabling electrical wire connections to the interconnecting copper metallization of ICs is formed. The structure comprises a layer of barrier metal, preferably nickel, that resists copper diffusion, deposited on the non-oxidized copper surface. The structure further comprises an outermost bondable metal layer, preferably gold, unto which a metal wire is bonded for metallurgical connection.

Nickel plating process having controlled hydrogen concentration

A semiconductor assembly comprising a semiconductor chip having an active and a passive surface, said active surface including an integrated circuit and a plurality of bonding pads; said bonding pads having a metallization suitable for wire bonding; an array of interconnects of uniform height, each of said interconnects comprising a wire loop substantially perpendicular to said active surface, each of said loops having both wire ends attached to a bonding pad, respectively, and a major and a minor diameter, said loops being oriented parallel with regard to the plane of the opening and having constant offsets in both direction and magnitude of their apex relative to their bonding pad centers; said wire loops having sufficient elasticity to act as stress-absorbing springs; an electrically insulating substrate having first and second surfaces, a plurality of electrically conductive routing strips integral with said substrate, and a plurality of contact pads disposed on said first surface, with attachment material disposed on each of said contact pads; each contact pad being attached to one of said wire loops, respectively, such that electrical contact between said chip and said substrate is established, while forming a gap therebetween having a width of approximately said major loop diameter; encapsulation material within said gap; a plurality of contact pads disposed on said second surface of said substrate; and solder balls attached to each of said contact pads disposed on said second surface of said substrate.

Wire bonded flip-chip assembly of semiconductor devices

A system (270, 370) for connecting a semiconductor chip (22, 322) to a leadframe (12), the system (270, 370) includes a three-dimensional leadframe (12) and a bonding support mechanism (202, 302, 402). The leadframe (12) may include a first lead (32, 132, 332, 432) having a first base portion (144), a first lead tip (42, 142, 342, 442), and a first longitudinal axis (305); a second lead (30, 130, 330, 430) having a second base portion (140, 321), a second lead tip (36, 136, 336, 436), and a second longitudinal axis. The first lead (32, 132, 332, 432) and second lead (30, 130, 330, 430) formed substantially adjacent to each other, and the second lead (30, 130, 330, 430) having a stepped portion (38, 138, 338, 438) such that the lead tips (42, 142, 342, 442, 36, 136, 336, 436) of the first lead (132, 332, 432) and second lead (130, 330, 430) are separated in a Z-direction (52) and in a Y-direction (52). The bonding support mechanism (202, 302) for holding the three-dimensional leadframe (12) may include a support body (215, 315), a trough (203, 303) formed on the support body (215, 315). The trough (203, 303) may have a first surface (204, 304) at a first elevation, where the first surface (204, 304) is for supporting the second lead tip (36, 136, 336). A second surface (206, 306) may be formed on the support body (215, 315) at a second elevation and substantially adjacent to the first surface (204, 304). The second surface (206, 306) is for supporting the first lead tip (42, 142, 342). The first elevation and second elevation may be displaced from each other. The bonding support mechanism (202, 302) may have an angled surface (210, 310) for accommodating a stepped portion (38, 138, 338, 438) of the second lead (30, 130, 330) and may have additional support surfaces (376, 319).

System, apparatus, and method for connecting a semiconductor chip to a

A method of using a single-headed bonder (80) to form bonds to bond pads (16) is provided. A single-headed bonder (80) includes a capillary (22) having a capillary face (40) with a long dimension along a first axis (BB) and a short dimension along a second axis (CC). The long dimension of the capillary face (40) is aligned in a first orientation such that the bond pads (16) are bonded in a first direction associated with the first orientation. The capillary (22) is then rotated to place the long dimension in a second orientation such that all the bond pads (16) are bonded in a second direction associated with the second orientation. In place of rotating the capillary (22), a second single-headed bonder (90) having a capillary (22) rotated to the second orientation can be used to bond bond pads (16) in the second direction. Transportation between bonders can be done manually, by a transport mechanism (60), by a robotic arm (70), or other suitable means.

Method for making an IC device using a single-headed bonder

A capillary tube (1) for bonding wire (5) has a bore (3) and a cross section in a direction normal to the bore having a long dimension and a short dimension in a direction normal to the long dimension. The bond is made to bond pads (9) using the capillary tube by bonding a wire to one bond pad while the capillary is oriented with the long dimension (25 to 27 or 35 to 37) in a first direction and bonding a wire to a die immediately adjacent the one bond pad with the capillary which can be oriented with the long dimension in the same direction or in a direction normal to the first direction, as may be required.

Capillary designs and process for fine pitch ball bonding

A method of producing a cavity package semiconductor device is disclosed. The method includes providing a bar pad having a plurality of bar pad straps, each strap extending outwardly from the outer edge of the bar pad and spaced about the edge of the bar pad; mounting integrated circuits having bond pads on the bar pad; molding a packing material onto a central portion of lead fingers and the bar straps to grip and surround each lead finger with package material, with a portion of each lead finger extending externally from the ring at both the exterior and interior thereof and to secure the bar pad straps therein; electrically coupling the bond pads to the portion of desired ones of the lead fingers extending toward the interior of the ring; and enclosing both ends of the ring to provide a cavity in the ring to suspend a bar pad with the integrated circuit thereon within the cavity with the bar pad straps.

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Plano, TX, United States of America

Howard Raeburn Test