International Business Machines Corporation

Other

Howard N Leighton

Raymond J Wilfinger

Christian A Jacquart

James F Dubil

Rene J Glaise

Michael M Siverling

Vladimir Riso

Alain M Falcoz

Raymond John Wilfinger

This specification describes a charge-transfer device transversal filter chip in which an input signal is fed in parallel into a number of channels the outputs of which are summed together to provide the desired transversal filter transfer function. Each channel contains an analog shift register, a signal splitter and a polarity selector. The shift registers are of unequal length to provide a different delay thru each channel. The signal splitter provides a plurality of signal paths thru each channel while the polarity selector determines whether a given path in a given channel is added or subtracted in the summation to determine the gain of the given channel in the summation.

Universal transversal filter chip

An array of optically sensitive devices senses printed matter with each device in the array producing an output signal representing a single black or white element in a multi-element picture being sensed by the whole array. These output signals are fed into an analog charge transfer shift register and passed serially in a fixed sequence through an output stage of the shift register. As the signal from each device passes through this output stage the device becomes what is hereafter referred to as the device of interest and the signal produced by it is analyzed to determine whether it is a black or white element. Other output stages simultaneously sense data from devices located around the device of interest to define a subarray within the original detected array while the last of these output stages is fed to a peak comparator to sense the brightest and darkest matter detected in the recent past by any element of the array. The results of these sensings are processed in accordance with a preselected algorithm to generate a digital signal wich is an indication of whether the device of interest has detected black or white. As the outputs of the array are shifted through the shift register each device of the array at one time or another is the device of interest of the subarray. The digital values of light intensity from all the devices in the array are then fed to a computer for analysis to determine what has been optically detected by the whole array.

Optical signal processor

A charge transfer device capacitive ratio voltage multiplication circuit has been devised which solves the problem of cumulative DC bias offset by adding a DC signal compensation branch to prevent the accumulation of DC offset potential. The circuit can be expanded to form a weighted sum of multiple inputs which does not incur any corresponding DC bias offset, by making the sum of the characteristic capacitances of each of the multiple inputs equal to the characteristic capacitance of the output portion of the charge transfer device circuit. The circuit allows arithmetic operations to be performed on input signals solely in the charge domain without the necessity of converting charge to voltage to charge, thereby avoiding losses, distortions, offsets and a reduction in dynamic range which would otherwise result.

Bucket brigade circuit for signal scaling

The underlying concept of the invention disclosed is the use of charge partitioning for providing a precision weighted tap in a bucket brigade circuit. At the drain node of a charge conducting element in a bucket brigade device, the signal path is split in half with a first half going to the source of a first FET and the second half going to the source of a second FET. The first and second FET devices have their associated overlap capacitances, transconductances and threshold voltages matched by virtue of their close proximity to one another on the semiconductor substrate so as to have matched charge transfer characteristics. The amplitude of the charge stored on the capacitor at the node is therefore divided into two parts, with one portion being transferred by the first FET device and the remaining portion being transferred by the second FET device. This simple circuit accomplishes a precise charge division for the charge entered into the bucket brigade circuit. Successive cells in the bucket brigade device can have their drain nodes connected to matched pairs of first and second FET devices to successively divide the charge stored therein by one-half so that a sequence of decrements in the charge transferred along the bucket brigade chain may be made in multiples of one-half. By selectively gating the outputs of each of the respective tapped branches from the bucket brigade device at a summing node, values of from zero to unity in fractional unit intervals can be generated as an analog output. A digital to analog converter may be formed by inputting a serialized digital word into the input of the bucket brigade device whose successive cells have attached thereto respective pairs of FET charge partitioning devices. The outputs of all branches are summed so that a resultant charge, which is the sum of the charges output by the charge partitioning transistors, will appear at the output as the analog value for the binary serial word input to the bucket brigade device.

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Rockville, MD, United States of America

Howard N Leighton