International Business Machines Corporation

Howard M Haynie

Jeffrey M Turner

Michael J Cadigan, Jr

Raymond Michael Higgs

Carl Alfred Bender

Clinton E Bubb

Nihad Hadzic

Michael Grassi

Jeffrey C Hanscom

Mushfiq U Saleheen

Kirk D Pospesel

Bruce H Ratcliff

Jie Zheng

Scot H Rider

Luke M Hopkins

Raymond Wong

Gabriel Martel Tarr

Donald Jung

Donald W Schmidt

Michael James Becht

Girish Gopala Kurup

Kathy Sue Barkey

Dan Vangor

Deepankar Bhattacharjee

Steven George Aden

Joel Goldman

Michael J Cardigan, Jr

Michael C Cadigan, Jr

Luke Hopkins

Embodiments of the present disclosure implement hardware-based snoop logic streaming timers for input/output (I/O) communications between a host and a shared network adapter in a computing system. The disclosed embodiments describe a hardware-based snoop logic and snoop logic timer function control of input/output (I/O) processor monitoring a defined memory area to detect a completion queue entry being written to a completion queue, and implementing streaming timers and interpacket timers, based on the completion queue entry and predefined configuration information for an associated host interface connection, to provide streaming data status, interpacket arrival times, and streaming timer expiration for the associated host interface connection.

Snoop logic function streaming timers

Systems and techniques for snooping input/output (I/O) events in a computing system are described. An example technique includes obtaining a configuration comprising a plurality of snoop space profiles, each snoop space profile indicating a respective range of memory addresses that map to a respective completion queue. The technique also includes monitoring input/output (I/O) traffic exchanged across a communication interface between an I/O adapter and a processor in a computing system, based on the configuration. The technique further includes performing one or more actions to assist processing of the I/O traffic, based in part on the monitoring.

Address based hardware snoop logic with configurable snoopable space settings for hardware assist

A method for updating a descriptor engine for a network interface card (NIT) can include quiescing, by a processing device, a transmit stream to the NIC. The method can further include stopping, by the processing device, a descriptor engine from providing new receive descriptors to the NIC. The method can further include setting, by the processing device, a controller to redirect inbound traffic to the memory. The method can further include restoring, by the processing device, a transmit configuration and a transmit state of the descriptor engine subsequent to updating the descriptor engine.

Upgrading a descriptor engine for a network interface card

A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Configurable hardware queue management and address translation

A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.

Hardware queue manager with water marking

A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Configurable hardware queue management

A method for updating a descriptor engine for a network interface card (NIC) may include quiescing a transmit stream to the NIC. The method may further include stopping a descriptor engine from providing new receive descriptors to the NIC. The method may further include creating a copy in a memory of any receive descriptors already available to the NIC prior to the stopping the descriptor engine. The method may further include setting a controller to redirect inbound traffic to the memory. The method may further include restoring a transmit configuration and a transmit state of the descriptor engine subsequent to updating the descriptor engine.

A method for facilitation of aggregation of contiguous data packets, such as contiguous I/O adapter stores, is disclosed. Commensurate with receiving data packets to be written to a memory, multiple contiguous data units of the data packets are aggregated into an aggregated data block. The aggregated data block is validated for writing to memory responsive to either the aggregated data block reaching a size which with inclusion of a next contiguous data unit in the aggregated data block would result in the aggregated data block exceeding a configurable size limit, or a next data unit of the plurality of data units to be written to memory being non-contiguous with the multiple contiguous data units.

Facilitating routing by selectively aggregating contiguous data units

Examples of techniques for upgrading a descriptor engine for a network interface card (NIC) are disclosed. An example method may include: quiescing a transmit stream to the NIC; stopping a descriptor engine from providing new receive descriptors to the NIC; creating a copy in a memory of any receive descriptors already available to the NIC prior to the stopping the descriptor engine; setting a controller to redirect inbound traffic to the memory; logging a current configuration, state, and receive pointers of the descriptor engine; updating the descriptor engine; restoring a transmit configuration and a transmit state of the descriptor engine; and enabling a transmit stream of a data router such that transmit packets are created by the descriptor engine for transmission by the NIC.

Embodiments relate to a method for encapsulating a hardware application for virtualization. The method surrounds the hardware application with a service layer controller and ring interfaces. The ring interfaces dictates a virtual function that the hardware application is running. The method controls the hardware application so that the hardware application is reset in between each of a plurality of running jobs. The method tags, by the ring interfaces, each of a plurality of requests with an identifier signifying a virtual function that the respective request belongs to. The method ensures that there are not any outstanding requests following a quiesce of the hardware application.

Encapsulation of an application for virtualization

Embodiments relate to a computer system comprising a service layer controller. The computer system comprises a ring interface unit configured to provide access to a host system that enables access to a plurality of virtual machines (VMs). The computer system comprises a hardware application configured to be encapsulated by the service layer controller such that the hardware application communicates to the host system via interfaces controlled by the ring interface unit and service layer controller.

A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.

Checksum calculation, prediction and validation

Embodiments relate to collecting extended error data from units within a programmable device. A pointer is accessed that points to a region of memory that contains a list of entries that references the extended error data. The list of entries is walked by adjusting a read pointer to obtain the extended error data. The referenced extended error data is moved to an event log.

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Wappingers Falls, NY, United States of America

Howard M Haynie