International Business Machines Corporation

Howard Lawrence Levy

Dung Q Nguyen

David R Terry

Steven J Battle

Salim Ahmed Shah

Saiful Islam

Eric Bernard Schorn

Sam G Chu

Binglong Zhang

An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.

Implementing write ports in register-file array cell

According to the present invention, a domino CMOS logic circuit having a plurality of stages for evaluating logic signals is provided. In one embodiment, the domino CMOS logic circuit includes at least one stage which has a logic block that includes a plurality of logic devices, inputs and outputs, and a precharge/evaluate circuit. In a more specific embodiment, the circuit includes a first transistor having a source connected to a supply voltage, a gate connected to a delayed clock signal, and a drain, a second transistor having a source connected to the drain of the first transistor, a gate connected to a clock signal, and a drain connected to the outputs of the logic block.

Method and apparatus for fast evaluation of dynamic CMOS logic circuits

A static XOR gate is provided with circuit speeds necessary to meet the increasing demand of higher computer clock frequencies. The XOR of the present invention takes up less area and consumes less power than prior art XOR circuits. Furthermore, time XOR gate of the present invention is fully static and imposes less constraints on the circuit designer, e.g. no reset logic, input synchronization, or the like. The circuit utilizes only NMOS transistors in the functional logic portion with two output inverters. The circuit elements are symmetrical and have identical input loading, output drive and propagation paths. The XOR of the present invention allows multiple gates to be connected in stages as a 'tree' configuration by providing a 'push-pull' XOR/EQV (equivalent, i.e. time complement of the XOR output or XNOR) function which is buffered by output inverters to 'push' the output to a next stage. Additional transistors are provided to help 'pull' internal nodes to the operating voltage but are not logically functional transistors. Further, input connections to the logical transistors are such as to eliminate unnecessary delay between like stages, when configured as a 'tree'.

Fast, low power exclusive or circuit

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Austin, TX, United States of America

Howard Lawrence Levy