Texas Instruments Corporation

Other

Howard L Tigelaar

Allan T Mitchell

James L Paterson

Andrew Marshall

Manzur Gill

Bert R Riemenschneider

Agerico L Esquivel

Cetin Kaya

Roger A Haken

Thomas C Holloway

Cloves Rinn Cleavelin

Robert Groover, Iii

Weize W Xiong

Richard L Guldi

Stephanie Watts Butler

George R Misium

Kalipatnam V Rao

Shaym G Garg

Theodore Warren Houston

Mehrdad M Moslehi

Amitava Chatterjee

Shivaling S Mahant-Shetti

Chih-Chen Cho

Richard A Stoltz

Ricky A Jackson

David K Liu

Richard A Chapman

Gabriel George Barna

Mark G Harward

Andrew T Appel

Toan Tran

Victor C Sutcliffe

Leif Christian Olsen

Abha Rani Singh

Robert G Fleck

Olivier Alain Faynot

Anand J Reddy

Melissa M Hewson

Cheing-Long Chen

Mauzur Gill

Bert R Riemenschnschneider

One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Semiconductor interconnect

A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region. The transistor gate and thus the transistor and the control gate are capacitively coupled to one another by at least one MOS coupling capacitor, with one plate of the MOS coupling capacitor ohmically coupled to or including the second semiconducting region.

SOI MuGFETs having single gate electrode level

One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.

Memory device with memory cell including MuGFET and FIN capacitor

A semiconductor device includes a gate electrode having ends that overlap isolation regions, wherein the gate electrode is located over an active region located within a semiconductor substrate. A gate oxide is located between the gate electrode and the active regions, and source/drains are located adjacent the gate electrode and within the active region. An etch stop layer is located over the gate electrode and the gate electrode has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that in one embodiment overlies the active region, and in another embodiment is less than one alignment tolerance from the active region.

Semiconductor device having improved gate electrode placement and decreased area design

An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

System and method for increasing the extent of built-in self-testing of memory and circuitry

Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes a local interconnect configured to electrically connect an output of a CMOS inverter to another circuit in the integrated circuit. Additionally, the feedback structure also includes an interconnect extension to the local interconnect configured to proximately extend along a gate structure of the CMOS inverter to provide a reactive coupling between the output and the gate structure.

Feedback structure for an SRAM cell

Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.

Dummy active area implementation

Memory device with memory cell including MuGFET and fin capacitor

One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a charge or voltage. The capacitor includes a first semiconductor fin having a first conductivity type and overlying a semiconductor body, a dielectric overlying at least part of the semiconductor fin, and a gate electrode overlying the dielectric. The memory cell also includes a diode. The diode includes an end portion of the first semiconductor fin and a second semiconductor fin that forms a junction with the end portion of the first semiconductor fin. The second semiconductor fin has a second conductivity type and includes first and second legs in different directions from the junction. Other devices and methods are also disclosed.

Memory device with capacitor and diode

A method () of forming fully-depleted silicon-on-insulator (FD-SOI) transistors () and bulk transistors () on a semiconductor substrate () as part of an integrated circuit fabrication process is disclosed.

Building fully-depleted and bulk transistors on same chip

A method () of forming fully-depleted silicon-on-insulator (FD-SOI) transistors () and partially-depleted silicon-on-insulator (FD-SOI) transistors () on a semiconductor substrate () as part of an integrated circuit fabrication process is disclosed.

Building fully-depleted and partially-depleted transistors on same chip

A method () of forming fully-depleted () and partially-depleted () silicon-on-insulator (SOI) devices on a single die in an integrated circuit device () is disclosed using SOI starting material () and a selective epitaxial growth process ().

Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices

A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

Sensitive test structure for assessing pattern anomalies

A gate structure () is formed on a semiconductor (). Source and drain extension regions () are formed in the semiconductor () adjacent to the gate structure (). Metal silicide layers () are formed on the extension regions () and sidewall structures (, and) are formed over the metal silicide layers (). Source and drain regions () are formed in the semiconductor (), and metal silicide layers () are formed on the source and drain regions ().

Integrated circuit MOS transistor with reduced drain and source resistance

Growing community of inventors

Allen, TX, United States of America

Howard L Tigelaar