Micron Technology Incorporated

Nan Ya Technology Corporation

Boise Technology, Inc.

Mcron Technology, Inc.

Howard Kirsch

Charles L Ingalls

Tae Hyoung Kim

David L Pinney

Werner Juengling

Sei Seung Yoon

Luan C Tran

Christopher John Kawamura

Mark D Durcan

Chandra V Mouli

Jun Liu

Scott James Derner

Michael P Violette

Di Li

J Wayne Thompson

K Shawn Smith

Jeremy J Gum

Gurtej S Sandhu

Todd A Merritt

H Montgomery Manning

Tyler J Gomm

Shubneesh Batra

Shigeki Tomishima

Chih-Chen Cho

Xianfeng Zhou

Zhong-Yi Xia

Michael V Cordoba

Frank Alejano

George B Raad

Huy Thanh Vo

Jonathan T Doebler

Vikram K Bollu

Jonathan L Gossi

Yu-Wen Huang

Mingshiang Wang

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. For example, a memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line&#x2014;e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased.

Boosting a digit line voltage for a write operation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. A memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line&#x2014;e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased.

A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

Double gated 4F2 dram CHC cell and methods of fabricating the same

Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers

Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

Memory device word line drivers and methods

Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline drivers coupled between a global wordline and the wordline. The plurality of local wordline drivers are configured to selectively couple the wordline to the global wordline during a memory access operation. The example apparatus further includes a global wordline driver configured to selectively couple the wordline to the global wordline during the memory access operation.

Apparatuses and methods for driving a voltage of a wordline of a memory

A pre-charging method applied in DRAM which includes steps of: enabling wordlines in an active array and an reference array; disabling the wordlines in the active array; equilibrating digital lines in the active array and the reference array to half of a power supply voltage; storing the half of the power supply voltage in reference cells of the reference array; disabling the wordlines in the reference array; pre-charging the digital lines in the active array and the reference array to the power supply voltage; and enabling the wordlines in the active array and the reference array at the same time.

Pre-charging method applied in dynamic random access memories

Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.

Apparatuses and methods for adjusting deactivation voltages

Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. During an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value of the charge stored by the memory cell. After the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value of the charge stored by the memory cell.

Apparatuses and methods for reducing current leakage in a memory

Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.

Data line control for sense amplifiers

Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

Line driver circuits, methods, and apparatuses

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Eagle, ID, United States of America

Howard Kirsch