International Business Machines Corporation

Other

Howard Harold Smith

Allan Harvey Dansky

Alina Deutsch

Peter J Camporese

Gerard Vincent Kopcsay

Michael Alexander Bowen

Barry Jay Rubin

Christopher J Berry

Wiren Dale Becker

Byron Lee Krauter

Alan P Wagstaff

Dale E Hoffman

Erich C Schanzenbach

Kwok Fai Eng

Anurag P Umbarkar

Raju Balasubramanian

Richard P Underwood

Bhupindra Singh

Phillip John Restle

David J Widiger

Fadi Y Busaba

Moises Cases

Joachim Keinert

Ibrahim M Elfadel

Matthew S Angyal

Peter Feldmann

Patrick M Williams

Albert E Ruehli

Minakshisundaran Balasubramanian Anand

Ching-Lung L Tong

Adrian Zuckerman

Rolf H Nijhuis

Glenn E Christensen

Ink refill cartridge for writing instrument

A method and system for implementing automated identification of optimal sense point (SP) and sector locations in various on-chip linear voltage regulator designs. A customized cost function is used along with predefined performance metrics to identify optimal SP and sector locations, under user-defined design constraints. The SP and sector locations are updated based on the identified optimization results, and the updated SP and sector locations are applied to an on-chip linear voltage regulator design to provide enhanced regulator performance and to ensure proper operation.

Implementing automated identification of optimal sense point and sector locations in various on-chip linear voltage regulator designs

A linear circuit simulator can be supplied with a linear power distribution model of an integrated circuit (IC) and two sets of voltage regulator equivalent resistances. The linear circuit simulator can then be used to calculate two voltages, at a sense point of the IC, corresponding to the two sets of voltage regulator equivalent resistances. The two sets of voltage regulator equivalent resistances and the two voltages at the IC sense point can be used to interpolate a slope of a resistance versus voltage curve of the linear power distribution model. The slope can be used to calculate an updated set of voltage regulator equivalent resistances, which can be used by the linear circuit simulator to calculate a set of performance metrics and an updated voltage at the sense point of the IC.

Evaluating on-chip voltage regulation

The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density in the at least one interconnect to an effective local maximum current density limit of the at least one interconnect.

Method and system for electromigration analysis on signal wiring

An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs:

Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques

Finger sheath with retractable stylus

This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques;

Decoupling capacitance analysis method

New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs:

Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques

A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.

Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures

This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques:

A system and method for analyzing a circuit with transmission lines includes determining which sources influence each of a plurality of transmission lines, based on coupling factors. Transmission line parameters are computed based on the sources, which influence each transmission line. A transient response or frequency response is analyzed for each transmission line by segmenting each line to perform an analysis on that line. The step of analyzing is repeated using waveforms determined in a previous iteration until convergence to a resultant waveform has occurred.

System and method for efficient analysis of transmission lines

Growing community of inventors

Beacon, NY, United States of America

Howard Harold Smith