Deltec Electronics Corporation

Datapower, Inc.

Industrial Design Associates, (ida)

Intelite Inc.

Howard Handler

Dale E Folwell

Ronald L Wilson

A crest factor correction circuit for an ac inverter receives inputs including a full-wave rectified output of the ac inverter having a fixed period and a periodic sequence of phase signals that divide each fixed period into predetermined phase intervals. An amplitude and crest factor signal circuit responds to the absolute value signal to provide an amplitude control signal proportional to the negative integral of the difference between the absolute value signal and a set reference voltage. The amplitude and crest factor signal circuit also provides a crest control signal proportional to the negative integral of the difference between the filtered peak value of the absolute value signal and a given reference voltage times a predetermined gain. A series resistor network responds to the amplitude control signal and to the crest control signal and provides a series of tap signals. Each tap signal is proportional to a respective predetermined ratio of the amplitude control signal. The series resistor network also provides a series of crest tap signals. Each crest tap signal is proportional to a respective predetermined ratio of the crest control signal. A multiplexer responds to the predetermined periodic series of phase signals, to the periodic series of tap signals and to the periodic series of crest tap signals to sequentially coupling a first sequence of the tap signals to an output terminal followed by coupling a sequence of crest tap signals to the output terminal followed by coupling a second sequence of the tap signals to the output terminal. The periodic sequence of tap signals and crest tap signals form the composite control signal for controlling the ac inverter.

Crest factor correction circuit

A crest factor correction circuit for an ac inverter receives inputs including a full-wave rectified output of the ac inverter having a fixed period and a periodic sequence of phase signals that divide each fixed period into predetermined phase intervals. An amplitude and crest factor signal circuit responds to the absolute value signal to provide an amplitude control signal proportional to the negative integral of the difference between the absolute value signal and a set reference voltage. The amplitude and crest factor signal circuit also provides a crest control signal proportional to the negative integral of the difference between the filtered peak value of the absolute value signal and a given reference voltage times a predetermined gain. A series resistor network responds to the amplitude control signal and to the crest control signal and provides a series of tap signals. Each tap signal is proportional to a respective predetermined ratio of the amplitude control signal. The series resistor network also provides a series of crest tap signals. Each crest tap signal is proportional to a respective predetermined ratio of the crest control signal. A multiplexer responds to the predetermined periodic series of phase signals, to the periodic series of tap signals and to the periodic series of crest tap signals to sequentially coupling a sequence of the tap signals followed by coupling a sequence of crest tap signals. The periodic sequence of tap signals and crest tap signals form the composite control signal for controlling the ac inverter.

A high frequency ballast circuit powered by a dc input voltage source for starting and operating a gas discharge lamp load, comprising: a means for providing drive signals, each the drive signal having a first and second state, a series switch having a conduction channel having a first and second terminal, the series switch having a control terminal responsive to the drive signals, the conduction channel is on (conductive) in responsive to the interval characterized by the first state of the drive signal and off (non-conductive) in response to a drive signal having a second state, and an inductor. A clamp diode is included. The inductor is coupled to the clamp diode cathode and to the series switch. A ballast reactance is included with a a power oscillator circuit, the power oscillator circuit has a transformer having, a primary winding having a first, a second and a center-tap terminal, a drive winding having a first and a second and a center-tap terminal, and an output winding. A reactance tunning means coupled between the transformer primary winding first and second terminal, a first and second drive switch, the primary winding first terminal is coupled to the first drive switch, the primary winding second terminal is coupled to the second drive switch, and the primary winding center-tap is coupled to the inductor; the drive winding first and second terminal are respectively coupled to the first and second a switch control terminals. A boost circuit means, and a timer circuit operating from the boost circuit means power, and means for adjusting the duty cycle ratio of the timer circuit.

High frequency ballast circuit

A high frequency ballast circuit is provided having first and second power input terminals and first and second power output terminals. The high frequency ballast circuit is powered by an input voltage source, such as an off-line, filtered, rectified dc voltage source. The high frequency ballast circuit has a starting mode and operating mode. The high frequency ballast circuit comprises: a power oscillator circuit having power oscillator first and second output terminals, for converting power coupled from the high frequency ballast circuit first and second power input terminals to a relatively high frequency, quasi-sinusoidal, current-limited voltage source applied between the power oscillator first and second output terminals. A starting circuit for interposing a periodic voltage pulse between the power oscillator first output terminal and the lamp load. The periodic voltage pulse is adapted to exceed the ionization potential of the lamp load during the starting mode. The starting and current limiting circuit also provides a predetermined reactance between the first power oscillator output terminal and the high frequency ballast circuit first power output terminal to limit current through the fluorescent lamp load. In an alternative embodiment, the starting and current limiting circuit is further adapted to interrupt the periodic voltage pulse during the operating mode. In another alternative and particularly preferred embodiment, the starting and current limiting circuit uses a SIDAC device and provides start pulses to the lamp load at approximately one second intervals until the lamp load ionizes.

A gas discharge lamp is connected across an inductor and in series with a solid state switching device and a resistor, and this combination is connected across a rectified AC voltage source. This switching device is controlled by a monostabile multivibrator, the input of which is connected to the output of a comparator amplifier sensing the difference between the voltage drop across the above-mentioned resistor and a voltage which may be selected to vary light intensity. The secondary winding of a step-up transformer connected to a capacitive discharge device is placed in series with the lamp. Control circuitry is provided to apply a large ignition voltage to the lamp while preventing damage to the switching device by simultaneously holding it in its conductive state. A diode rectifier provides an alternate current path across the secondary winding to prevent the inductance of the secondary winding from affecting normal lamp operation. Means are provided to cancel the contribution of lamp current to the voltage drop across the resistor sensed by the comparator, thereby rendering power consumed by the circuit independent of the effective resistance of the lamp.

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Westminster, CA, United States of America

Howard Handler