Lattice Semiconductor Corporation

Applied Materials, Inc.

Howard H Tang

San-Ta Kow

Roger Spinti

Om P Agrawal

Fabiano Fontana

Peijun Ding

Ju Shen

Ann Wu

Tony P Chiang

Jianming Fu

David Lee Rutledge

Satwant Singh

Jack Tim Wong

Anish Tolia

Henry Law

Yu D Cong

Clark Wilkinson

Jeffrey S Byrne

Imran Hashim

Michael A Miller

Cyrus Y Tsui

James S Van Gogh

Richard Hong

Mark Lloyd

Fernand Dorleans

Jeff Byrne

Christopher Hagerty

Siyaun Yang

R Steve West

Daniel V Parker

In one embodiment, a programmable logic device includes configuration memory, an SPI port for receiving a bitstream, a chip select output pin, and configuration control circuitry. The chip select output pin can provide a chip select signal having a first logic state for selecting another device (such as another PLD) to receive a bitstream and a second logic state for de-selecting the other device. The configuration control circuitry is responsive to a command embedded in the received bitstream to drive the chip select output pin from the second logic state to the first logic state, thereby selecting the other device to receive the bitstream. Several such PLDs connected in a daisy chain can thus be configured from a single configuration source or have their configuration data read back while so connected.

Configuring multiple programmable logic devices with serial peripheral interfaces

In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes transferring the configuration data from non-volatile memory to configuration memory within the programmable logic device; calculating a code value based on the configuration data transferred from the non-volatile memory to the configuration memory; and comparing the calculated code value to the pre-calculated code value.

Programmable logic device programming verification systems and methods

Various techniques are described to provide an internally triggered reconfiguration of a programmable logic device (PLD). In one example, a PLD includes configuration memory adapted to store first configuration data to configure the PLD for its intended function. The PLD also includes a bus interface adapted to interface with configuration data storage memory. The PLD further includes user logic configured by the first configuration data and adapted to provide a reconfiguration signal to trigger a reconfiguration of the PLD. In addition, the PLD includes a bus interface controller responsive to the reconfiguration signal for loading second configuration data from the configuration data storage memory via the bus interface.

Internally triggered reconfiguration of programmable logic devices

In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preamble as the first bitstream is read from the non-volatile memory and before configuration data in the first bitstream is programmed into the volatile configuration memory. If a valid preamble is detected in the first bitstream, the controller programs the configuration memory with configuration data in the first bitstream. If a valid preamble is not detected in the first bitstream, the controller reads a second bitstream from a second memory block of the non-volatile memory.

Programmable logic device and methods for providing multi-boot configuration data support

In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

Flexible memory architectures for programmable logic devices

Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.

Register data retention systems and methods during reprogramming of programmable logic devices

In embodiment of the invention, a programmable logic device includes configuration memory adapted to be programmed with configuration data and a plurality of programmable fuses adapted to store a security key for use with configuration data. The security key includes a plurality of data bit values, wherein each data bit value of the security key is associated with a subset of a least three fuses each storing a bit. Each of a plurality of decoders is adapted to retrieve a data bit value of the security key by providing the bit value stored by a majority of the fuses of the associated subset as the data bit value of the security key.

Method and devices for storing a security key using programmable fuses

In one embodiment, a programmable logic device (PLD) includes a slave port and a master port. The slave port can receive a configuration data bitstream and a slave clock signal from a master port of a first external device. The master port can provide the configuration data bitstream and a master clock signal from the PLD to a slave port of a second external device. An interface block in the PLD can pass the configuration data bitstream from the slave port through the PLD to the master port. In another embodiment, a PLD includes a slave serial peripheral interface (SPI) port and configuration memory. The slave SPI port can receive a configuration data bitstream and a slave clock signal from a master SPI port of an external device. The configuration memory stores the received bitstream for configuring the PLD.

Programmable logic device providing serial peripheral interfaces

In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks adapted to precondition registers within the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.

Transparent field reconfiguration for programmable logic devices

In accordance with an embodiment of the present invention, a programmable logic device includes configuration memory to store configuration data to configure the programmable logic device, and a non-volatile memory to store configuration data for transfer to the configuration memory to configure the programmable logic device. The non-volatile memory also stores a first code value based on the configuration data stored in the non-volatile memory. A code block calculates a second code value based on the configuration data transferred to the configuration memory. A comparator compares the first code value to the second code value to verify that the configuration data was not corrupted during the transfer from the non-volatile memory to the configuration memory.

In one embodiment, a programmable logic device includes a first multiplexer; a first memory adapted to store an identification code of the programmable logic device; and a second memory adapted to store an identification code of the programmable logic device. Inputs of a second multiplexer are coupled to the first memory and the second memory, and an output of the multiplexer is coupled to an input of the first multiplexer. The second multiplexer is adapted to select between the identification code stored in the first memory and the identification code stored in the second memory to provide the selected identification code to the first multiplexer.

Programmable logic devices with custom identification systems and methods

Systems and methods are disclosed herein to provide improved security key techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a method of providing data security for a programmable logic device (PLD) includes programming a plurality of programmable fuses that stores a security key comprising a plurality of data bit values, wherein each data bit value is associated with a respective subset of at least three of the fuses. The security key is retrieved from the fuses using the data bit values stored by each subset of the fuses. An encrypted configuration data bitstream is decrypted using the retrieved security key to obtain an original configuration data bitstream to configure the PLD.

Methods and systems for storing a security key using programmable fuses

Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks and corresponding input/output pins, and configuration memory. The PLD also includes registers adapted to capture output signal values of the input/output pins before a reconfiguration of the programmable logic device and to provide the captured values on the input/output pins during the reconfiguration of the PLD.

Reconfiguration of programmable logic devices

Various techniques are disclosed herein to provide an improved approach to the loading of configuration data into configuration memory of programmable logic devices. For example, in accordance with one embodiment of the present invention a method of configuring a programmable logic device includes reading a first bitstream from a first memory block of an external memory device. The first bitstream is checked for errors and a second bitstream is read from a second memory block of the external memory device if an error is detected. Configuration memory of the programmable logic device is programmed with configuration data provided in one of the first bitstream and the second bitstream.

Programmable logic device methods and system for providing multi-boot configuration data support

Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). In one example, a method of operating a PLD includes receiving a configuration data bitstream at a slave serial peripheral interface (SPI) port of a PLD from a master SPI port of a first external device. The method also includes passing the configuration data bitstream through the PLD from the slave SPI port of the PLD to a master SPI port of the PLD. The method further includes providing the configuration data bitstream from the master SPI port of the PLD to a slave SPI port of a second external device.

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San Jose, CA, United States of America

Howard H Tang