Cirrus Logic Inc.

Other

Howard H Sheerin

Neal Glover

William G Bliss

Paul M Romano

Mark S Spurbeck

John J Schadegg

A method of configuring an online account of a user is disclosed. A service provider receives a public cryptocurrency address from a user's computer and associates the public cryptocurrency address with the online account of the user. The service provider establishes a secure communication session between the user's computer and the service provider based on the user logging into a first area of the online account of the user. After establishing the secure communication session, the service provider determines that a second area of the online account is in a locked state. The service provider determines that the user has reduced a balance associated with the public cryptocurrency address during the secure communication session, and in response to determining that the balance associated with the public cryptocurrency address has been reduced during the secure communication session, unlocks the second area of the online account.

Locking an online account based on a public cryptocurrency address

A magnetic disc storage system employing two stage actuators for simultaneously positioning recording heads over the top and bottom surfaces of the disc is disclosed. The recording heads are fastened to a distal end of respective top and bottom load beams. A base end of the load beams is connected to a voice coil motor (VCM) rotary actuator which simultaneously positions both recording heads over the disc. A silicon microactuator is also fastened to the distal end of at least one of the load beams for positioning the recording heads independent of one another, thereby allowing simultaneous tracking of embedded servo data. Various data formats are provided, including interleaving logical sector numbers, symbols of a logical sector, and segments of a logical sector, between the top and bottom physical sectors of a track. Complexity and cost of the servo controllers is reduced through the use of sliding mode control: a simple, robust and fast control system implemented using simple switching circuitry, small lookup tables, and simplified binary multipliers (shift registers). A dual path read channel implemented in a single integrated circuit is provided for parallel processing the read signals from the top and bottom recording heads.

Magnetic disc recording system employing two stage actuators for

In a disc storage system employing multiple recording heads to increase throughput by providing simultaneous access through multiple data streams, a sampled amplitude read channel is disclosed for detecting, in parallel, estimated data sequences from the read signals associated with each data stream. Timing recovery in the read channel is implemented through interpolation, that is, by asynchronously sampling the analog read signals and interpolating to synchronous sample values. In this manner, a frequency synthesizer can generate a single reference clock for clocking operation of all the discrete time circuitry, thereby eliminating noise caused by multiple clocks as well as simplifying diagnostics. Furthermore, interpolated timing recovery avoids noise due to cross-talk between voltage controlled oscillators (VCOs) that would likely occur in a conventional synchronous sampling timing recovery design. A significant advantage is that the read channel can reside in a single integrated circuit.

Sampled amplitude read channel for processing multiple data streams in a

A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a synchronous data clock for clocking a discrete time sequence detector and pulse detector which detect the digital user and servo data from the interpolated sample values.

Fixed sample rate sampled amplitude read channel for zoned magnetic

A method and apparatus for programming a home answering machine having multiple storage devices for individual voice mail boxes and capable of receiving 'Caller ID' data. The answering machine is programmed either by the caller or the user so that the 'Caller ID' data can be used to automatically route incoming messages to individual voice mail boxes. A caller identification data base stores the 'Caller ID' data, and a CPU uses the data base to direct the caller's message to the appropriate voice mail box.

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Denver, CO, United States of America

Howard H Sheerin