Intergraph Corporation

Telairity Semiconductor, Inc.

Howard G Sachs

James Y Cho

Siamak Arya

Walter H Hollingsworth

A group based design methodology and system. In one embodiment the groups have predefined layout characteristics and are sometimes amalgamated into functions. Integrated circuits are designed by placing groups and functions into a layout space.

Circuit group design methodologies

A system is disclosed for use of imperfect ROMs in embedded systems. The ROM or other memory accessible upon start-up of the system, includes a stored program which checks an external source to determine whether any of the information in the ROM should be replaced. If it should be replaced, then the system retrieves good information from an external source and stores it into a cache memory. By setting a 'lock' bit, erasure of the replacement information is prevented.

System for repair of ROM programming errors or defects

A state machine provides a power reducing capability by turning off a clock signal to a memory which stores the state of the state machine. Preferably, the state machine is connected to receive information from an external circuit, typically a system to be controlled by the state machine. The state machine includes a programmable memory in which each row stores a word representing output information as a sequence of bits. It also includes a register which stores the state of the state machine when the memory is not active. The state machine includes a selection circuit which selects a next state of the state machine. When the next state of the state machine is selected to be the same as the previous state the clock signal to the memory is turned off, enabling reduced power consumption by the state machine.

Idle power reduction for state machines

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Instruction cache association crossbar switch

VLIW processor and method therefor

Instruction cache associative crossbar switch

An address translation memory stores a plurality of virtual address tags. The virtual address tags typically designate a portion of the virtual address space corresponding to a page of data stored in an intermediate storage device. A portion of an input virtual address is used to address the translation memory, and the resulting output virtual address tag is compared to a relevant portion of the input virtual address. If they match, then the requested data resides in the intermediate storage device, and an instruction issuing unit allows the instructions to continue issuing to an instruction pipeline as scheduled. However, if the virtual address tag does not match the relevant portion of the input virtual address, then it is assumed that a page fault might occur, and the instruction issuing unit inhibits the issuance of further instructions to the instruction pipeline. A page table stored in the second storage memory is then accessed to determine whether in fact the page corresponding to the input virtual address is stored in the second storage device. If so, then the instruction issuing unit resumes issuing instructions to the instruction pipeline. If not, then the page corresponding to the input virtual address is retrieved from first storage device and communicated to the second storage device, and the instruction issuing unit resumes issuing instructions to the instruction pipeline.

Method and apparatus for controlling an instruction pipeline in a data processing system

Method and apparatus for controlling an instruction pipeline in a data

Instruction cache associative crossbar switch system

A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be executed in parallel are identified. The system includes a register for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags and group identification tags indicative of the pipeline to which they should be dispatched, and the group of instructions which may be dispatched during the same operation. The pipeline and group identification tags are used to dispatch the appropriate groups of instructions simultaneously to the differing pipelines.

Software scheduled superscalar computer architecture

An adder adds a displacement address to a base address to generate a virtual address. The adder includes carry indicating circuitry for generating a carry indicating signal indicating whether the addition of the displacement address to the base address resulted in a carry. Addressing circuitry addresses the translation memory with a subset of bits from the base address so that the translation memory outputs multiple address translation entries simultaneously. At approximately the same time the translation memory outputs the multiple address translation entries, the adder completes the addition of the displacement address to the base address and generates the carry indicating signal. A multiplexer selects one of the address translations output from the translation memory in response to the carry indicating signal.

Apparatus for obtaining data from a translation memory based on carry

A computing system has multiple instruction pipelines, wherein one or more pipelines require translating virtual addresses to real addresses. A TLB is provided for each pipeline requiring address translation services, and an adress translator is provided for each such pipeline for translating a virtual address recieved from its associated pipeline into corresponding real addresses. Each address translator comprises a translation buffer accessing circuit for accessing the TLB, a translation indicating circuit for indicating whether translation data for the virtual address is stored in the translation buffer, and an update control circuit for activating the direct address translation circuit when the translation data for the virtual address is not stored in the TLB. The update control circuit also stores the translation data retrieved from the main memory into the TLB. If it is desired to have the same translation information available for all the pipelines in a group, then the update control circuit also updates all the other TLB's in the group.

Method and apparatus for translating virtual addresses in a data

A Cache-Memory Management System provides high speed virtual to real address translation. Address translation logic, comprised of mutually exclusive modifiable and nonmodifiable translation logic, selectively provides real address output responsive to the externally supplied virtual address from the processor. The modifiable translation logic includes modifiable read-write memory, while the non-modifiable translation logic includes fixed combinational logic for providing predefined translations of predetermined virtual addresses to real addresses. A controller selectively accesses main memory on cache memory misses to load translation information and other data from main memory to the cache memory. In a preferred embodiment, the address translation logic provides an associated system tag defining access priorities and access modes with each address translation.

Memory address translation system having modifiable and non-modifiable

A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache-memory management system. The cache-memory management system provides high speed virtual to real address translation along with associated system tag data defining access priorities and access modes associated with each respective address translation. The selectable access modes provides software definable features, such as cacheable data or non-cacheable data, write-through or copyback main memory update strategies for cacheable data, and real memory address space selection as main memory real address space, versus Boot ROM real address space versus input/output real address space. Page tables are loaded into main memory which contain address translation data and associated system tags. Upon initialization of the modifiable translation logic in the cache-memory management system, the address translations and associated system tags are loaded into the address translation logic of the cache-memory management system. Thereafter, as a part of the virtual to real address translation performed by the cache-memory management system, access modes and attributes are determined for each address translation, to provide for proper memory access of cacheable versus non-cacheable storage, etc., as part of the address translation and memory management function.

Growing community of inventors

Los Altos, CA, United States of America

Howard G Sachs