Micron Technology Incorporated

Omnivision Technologies, Inc.

Aptina Imaging Corporation

Round Rock Research, LLC

Other

Micron Semiconductor, Inc.

Howard E Rhodes

Hsin-Chih Tai

Duli Mao

Vincent Venezia

Yin Qian

Gurtej S Sandhu

Chandra V Mouli

Gang Chen

Philip J Ireland

Pierre C Fazan

Richard A Mauritzson

Sujit Sharan

Charles H Dennison

Kirk D Prall

Yauh-Ching Liu

Tyler A Lowrey

Sohei Manabe

Guy T Blalock

Vishnu Kumar Agarwal

Hiang C Chan

Rongsheng Yang

Hidetoshi Nozaki

Werner Juengling

Mark D Durcan

Ashish A Shah

Wei Zheng

Luan C Tran

Ravi T Iyer

Mark R Visokay

D Mark Durcan

Dan Gealy

Inna V Patrick

Randhir P S Thakur

Pai-Hung Pan

Aftab A Ahmad

Trung Tri Doan

Cem Basceri

Dyson Hsinchih Tai

Tiejun Dai

Keh-Chiang Ku

Kenneth N Hagen

Dale G Fried

James S Foresi

Stephen L Casper

Brian M Shirley

Robert B Kerr

Timothy J Allen

Sing-Chung Hu

Haining Yang

David F Cheffings

Fernando N Gonzalez

Randhir P Thakur

Martin Ceredig Roberts

Dajiang Yang

Lyle D Breiner

Sukesh Sandhu

Rod C Langley

Bryan G Cole

Steven D Cummings

Steve V Cole

Hongjun Li

Tom Graettinger

Steve Cummings

Sanh D Tang

Monte Manning

F Daniel Gealy

Richard H Lane

Thomas Arthur Figura

Thomas M Graettinger

Fred D Fishburn

Xiaofeng Fan

Jeffrey A McKee

Kenneth Kubala

Chen-Wei Lu

Eric A G Webster

Gary Lynn Duerksen

Jin Li

Gregory Johnson

Mark Anthony Meloni

Robert H Cormack

Dominic Massetti

Regis Fan

Cunyu Yang

Satoru Tachihara

Alan R Reinberg

Zhiqiang (Jeff) Wu

Jizhang Shan

Edward Raymond Dowski, Jr

Don Carl Powell

Sungkwon C Hong

Johannes Solhusvik

Paulo E X Silveira

Jeffrey L Morin

Jie Shen

David J Kubista

Jeff A Mckee

Goran Matko Rauker

Hongli Yang

Manoj Bikumandla

Jeong-Ho Lyu

A method of image sensor fabrication includes forming a second semiconductor layer on a back side of a first semiconductor layer. The method also includes forming one or more groups of pixels disposed in a front side of the first semiconductor layer. The one or more groups of pixels include a first portion of pixels separated from the second semiconductor layer by a spacer region, and a second portion of pixels, where a first doped region of the second portion of pixels is in contact with the second semiconductor layer. Pinning wells are also formed and separate individual pixels in the one or more groups of pixels, and the pinning wells extend through the first semiconductor layer. Deep pinning wells are also formed and separate the one or more groups of pixels.

Visible and infrared image sensor

Arrayed imaging systems include an array of detectors formed with a common base and a first array of layered optical elements, each one of the layered optical elements being optically connected with a detector in the array of detectors.

Arrayed imaging systems having improved alignment and associated methods

A pixel array including an SiGelayer disposed on a first semiconductor layer. A plurality of pixels is disposed in the first semiconductor layer. The plurality of pixels includes: (1) a first portion of pixels separated from the SiGelayer by a spacer region and (2) a second portion of pixels including a first doped region in contact with the SiGelayer. The pixel array also includes pinning wells disposed between individual pixels in the plurality of pixels. A first portion of the pinning wells extend through the first semiconductor layer. A second portion of the pinning wells extend through the first semiconductor layer and the SiGelayer.

A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate. Additionally, a second wafer is formed that includes a second semiconductor substrate and a second interconnect layer. A second insulation-filled trench is formed in a second semiconductor substrate, and the first wafer is bonded to the second wafer. A third interconnect layer of a third wafer is bonded to the second wafer. At least one deep via cavity is formed through the first and second interconnect layers and through the first and second insulation-filled trenches. The at least one deep via cavity is filled with a conductive material to form a deep via.

Method of fabricating multi-wafer image sensor

Embodiments of an image sensor pixel that includes a photosensitive element, a floating diffusion region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The floating diffusion region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region. The transfer device includes a buried channel device including a buried channel gate disposed over a buried channel dopant region. The transfer device also includes a surface channel device including a surface channel gate disposed over a surface channel region. The surface channel device is in series with the buried channel device. The surface channel gate has the opposite polarity of the buried channel gate.

Partial buried channel transfer device for image sensors

An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p&#xd7;q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.

Stacked chip shared pixel architecture

A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is coupled to selectively transfer the image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure disposed in the semiconductor material. The DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. The DTI structure includes a doped semiconductor material disposed inside the DTI structure that is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

Image sensor pixel cell with switched deep trench isolation structure

An example image sensor includes first, second, and third micro-lenses. The first micro-lens is in a first color pixel and has a first curvature and a first height. The second micro-lens is in a second color pixel and has a second curvature and a second height. The third micro-lens is in a third color pixel and has a third curvature and a third height. The first curvature is the same as both the second curvature and the third curvature and the first height is greater than the second height and the second height is greater than the third height, such that light absorption depths for the first, second, and third color pixels are the same.

Image sensor with color pixels having uniform light absorption depths

A method of fabricating an image sensor includes forming a pixel array in an imaging region of a semiconductor substrate and forming a trench in a peripheral region of the semiconductor substrate after forming the pixel array. The peripheral region is on a perimeter of the imaging region. The trench is filled with an insulating material. An interconnect layer is formed after filling the trench with insulating material. A first wafer is bonded to a second wafer. The first wafer includes the interconnect layer and the semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the insulating material. A via cavity is formed through the insulating material. The via cavity extends down to a second interconnect layer of the second wafer. The via cavity is filled with a conductive material to form a via. The insulating material insulates the conductive material from the semiconductor substrate.

An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.

Die seal ring for integrated circuit system with stacked device wafers

Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.

Dual-facing camera assembly

Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed.

Color filter including clear pixel and hard mask

Embodiments are disclosed of an apparatus comprising a color filter arrangement including a set of color filters. The set of color filters includes a pair of first color filters, each having first and second hard mask layers formed thereon, a second color filter having the first hard mask layer formed thereon, and a third color filter having no hard mask layer formed thereon. Other embodiments are disclosed and claimed.

Color filter patterning using hard mask

A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element.

Lateral light shield in backside illuminated imaging sensors

Growing community of inventors

Boise, ID, United States of America

Howard E Rhodes