Agilent Technologies, Inc.

Hewlett-packard Company

Hewlett-packard Corporation

Howard E Hilton

John H Guilford

Gerald J Ringel

David E Smith

Dennis Eugene Ochs

David Lynn Burton

George Stennis Moore

Edward L Feldhousen

J Daren Bledsoe

Brian D Setterberg

Darrin Dennis Rath

Yi He

Brian C Dunn

Dan D Danielson

Charles R Panek

John Albert Snodderley

David E Rasmussen

Brian Barton

Robert A Gilbert

An apparatus includes a global synchronization interface and multiple modules. The global synchronization interface includes a global synchronization driver for driving a global synchronization signal. The modules include corresponding local synchronization interfaces, each local synchronization interface having a local synchronization driver for driving a local synchronization signal. In a local mode, the modules ignore the global synchronization signal and synchronize corresponding operations according to the local synchronization signal and a global reference signal. In a global mode, the modules ignore the local synchronization signal and synchronize the corresponding operations according to the global synchronization signal and the global reference signal.

Method and apparatus for hierarchial system synchronization

A single finite impulse response filter designed to operate on a single signal is used in conjunction with an input multiplexer that interleaves samples from multiple signals and an output decimator. The output of the decimator contains interleaved samples of the multiple signals with independent filtering applied to each.

Efficient implementation of filters for MIMO fading

Pipelined digital accumulators. Parallel digital accumulators for use in digital signal processing are improved through pipelining. An accumulator is partitioned into a plurality of pipelined stages, and the pipeline delay is used to reduce the effect of carry propagation through the accumulator. While input and output delay registers are used in the accumulator partitions, the output delay registers are not needed if the results of those partitions are not needed in subsequent stages of computation. If phase coherence is not needed, input delay registers may not be needed on accumulator partitions. In the limiting case of one bit per partition, the effective speed of the pipelined accumulator is equivalent to the speed of a single bit accumulator stage.

Pipelined accumulators

Data values representing the (I+Q) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the histogram is stored in a memory. Each floating-point number acts as an address for a corresponding histogram bin in the memory. The accumulated counts in the histogram bins are then grouped into a desired number of CCDF bins, and the CCDF curve is derived from the histogram data. Grouping the histogram bins into the CCDF bins may include combining one or more histogram bins into a single CCDF bin. Linear interpolation is used to divide a count value in a histogram bin between two CCDF bins when the histogram bin does not align with a single CCDF bin.

Method and system for accelerating power complementary cumulative distribution function measurements

One embodiment of the invention includes a system comprising an analog baseband signal input, a conversion circuit with N Analog to Digital Converters (ADCs) operable to receive the analog baseband signal, and a Finite Impulse Response (FIR) filter operable to receive outputs of the N ADCs and to produce a digital representation of the analog baseband signal corrected for a mismatch in the N ADCs.

Sample rate doubling using alternating ADCs

In one representative embodiment, multiple ensembles of samples of a periodic or cylcostationary signal are processed in a time aligned manner. The sampling rate of the processing system is adjusted so that an integer number of sampling intervals equals the period of the signal. A cyclic counter is programmed to reset according to the integer number. Also, the cyclic counter may be initialized according to an external trigger. During operation, the cyclic counter is incremented when each sample is received. Continuous operation of the cyclic counter with the capturing of samples enables precise time alignment between ensembles of samples. Specifically, the beginning of a discrete ensemble is identified by a reset of the cyclic counter. Because each ensemble is time aligned, further processing (e.g., coherent averaging) may occur without post-processing to time-shift each sample to achieve the time alignment.

System and method for processing a periodic or cyclostationary signal

Correction of differences between two analog to digital converters (ADCs) in broadband intermediate frequency conversion. By stimulating a two-ADC system with a known input, the impulse response of the system is derived, and from that impulse response a finite impulse response filter is derived which corrects for mismatches between the ADCs.

Broadband IF conversion using two ADCs

A versatile signal generator for generating digitally modulated test signals computed in real-time is provided. Each of the blocks ol the versatile signal generator, including the MUX, coder, map, filter, re-sampler, and modulator, are implemented in a sufficiently flexible manner so as to allow ready configuration to produce any of a variety of digitally modulated signals as well as high quality analog modulated signals. Each of the blocks may be implemented using ASICs and RAM that allow to obtain high symbol rates while being capable of being reconfigured for different test signals as needed. The versatile signal generator has a real time input for receiving input data to modulate the test signal in real time.

Versatile signal generator

A phase detector for symbol clock recovery in a digital communications system determines the phase error of a local symbol clock from the symbol rate of a transmitted signal by sampling the transmitted signal to obtain a first sample at a fraction of a symbol period after the symbol clock and to obtain a second sample at an equal fraction of a symbol period before the symbol clock, and determining a phase error equal to the difference between a function of the magnitude of the first sample and a function of the magnitude of the second sample. The function is preferably the square of the magnitude or the logarithm of the magnitude of the samples.

Clock recovery phase detector

An ECG recorder and playback unit which includes software-implemented digital signal processing filters which compensate for phase and magnitude distortion occurring when an ECG signal is recorded on a Holter recorder and played back. This permits 'tuning' a recorder and playback unit which may be unrelated, as when made by different manufacturers. An impulse or step signal is recorded and played back to provide a system frequency response measurement. Coefficients for a digital correction filter are derived from the discrete Fourier transform of the impulse or step response and a desired system response. When recorded ECG data is played back, it is filtered on a substantially real-time basis with the digital correction filter to compensate for phase and magnitude distortion. Prior to recording, the high frequencies of the ECG signal are boosted to compensate for high frequency losses inherent in the recording and playing back of ECG signals. A calibration pulse and a system characterization pulse are derived by statistically selecting from a plurality of pulses and averaging the selected pulses in order to minimize the effects of noise and tape defects in the pulses. High frequency components of the ECG signal can be amplified prior to recording the signal. This results in decreased amplification, and therefore noise, when the recorded signals are played back. Cardiac pacer pulse detection is performed prior to the step of filtering the played back signal to optimize pulse detection.

ECG recorder and playback unit

A sensor is disclosed which exchanges with associated data acquisition equipment a digital attribute signal, distinct from its transducer output signal, on the occurrence of a predetermined event. The invention is particularly illustrated with reference to an accelerometer which transmits sensor identification data to associated data acquisition equipment when power is first applied by using the same two signal lines as are used to provide power to the sensor and to convey the sensor output signal to the equipment. After the identification data is transmitted, the apparatus operates as a buffer amplifier to modulate the transducer output signal onto the same two signal lines.

Improved sensor

Errors in a sampled data process are discerned statistically throughout the process, permitting their efficient removal. An exemplary application is a subranging analog-to-digital converter (ADC), in which errors associated with component digital-to-analog (DAC) current sources are discerned and corrected automatically during the circuit's normal operation. This is achieved by continually introducing a random signal into the process, statistically examining the DAC output signal to discern error terms, and correlating the occurrences of these errors with the values of the random signal applied to the DACs so as to identify the current sources to which the error terms are due. The resulting ADC output signal is compensated to remove the random signal and is further compensated to remove the DAC error terms discerned by this statistical analysis. The effect of any errors that may remain due to imperfect quantification of the DAC error terms is minimized due to their randomization, permitting the removal of these error terms by averaging techniques.

Statistically based continuous autocalibration method and apparatus

A signal receiver having a frequency selective sampling detector which accepts a bandlimited analog signal and outputs uniformly spaced, digital samples of the signal's quadrature and in-phase components. The center frequency, phase reference and sample interval for the detector are derived from a single reference clock. The bandwidth of the detector is variable while maintaining the same center frequency.

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Snohomish, WA, United States of America

Howard E Hilton