Montage Technology Co., Ltd.

Montage Technology Group Limited

Integrated Device Technology, Inc.

Montage Technology (shanghai) Co., Ltd.

Howard Chonghe Yang

Gang Shan

Yi Bu Li

Larry Wu

Stephen Tai

Chuen-Der Lien

Frank Hwang

Jimmy J Lee

Zhen-Dong Guo

Zhongyuan Chang

Xiaomin Si

Chunyi Li

YuFei Gu

Qing Ou-yang

An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.

Apparatus and method for controlling access to memory module

A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.

Memory controller and method for accessing memory module

The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Memory controller

A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.

Data conversion control apparatus, memory device and memory system

The application discloses a memory controller and a method for controlling an access to a memory module. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving data access command from the host controller and coupled to the memory module for providing an encrypted data access command to the memory module; wherein the central buffer comprises a command processing module, for performing encryption operation to a data access command with a predefined command encryption algorithm to generate an encrypted data access command; wherein a data channel is coupled between the memory module and the host controller, and wherein under the control of the encrypted data access command, the memory module exchanges data with the host controller via the data channel.

Memory controller, method for performing access control to memory module

Memory controller and method for accessing memory modules and processing sub-modules

The present application provides a memory module. The memory module includes one or more volatile memory devices, one or more non-volatile memory devices, and a data exchange controller. The data exchange controller controls data exchange between the volatile memory devices and the non-volatile memory devices.

Memory module and method for exchanging data in memory module

A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset value(s), and combinations of such.

Method and apparatus for clock generation

A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

Memory interface to bridge memory buses

A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.

High speed transceiver with low power consumption

Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.

On-chip supply regulators

A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset values(s), and combinations of such.

A voltage/current reference circuit includes a first bipolar transistor and a second bipolar transistor that exhibit a first voltage drop Vand a second voltage drop V, respectively. A first resistor, having a resistance R, is configured to draw a first current equal to (V&#x2212;V)/R. A second resistor, having a resistance R, is configured to draw a second current equal to V/R. A first transistor supplies the first and second currents to the first and second resistors. A second transistor, having a current mirror configuration with respect to the first transistor, directly provides a reference current equal to (V&#x2212;V)/R+V/R. A third transistor, having a current mirror configuration with respect to the first transistor, provides a current equal to the reference current to a third resistor having a resistance Rand a third bipolar transistor that exhibits a third voltage drop V, thereby generating a reference voltage.

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Shanghai, China

Howard Chonghe Yang