Intel Corporation

Howard Chen

Youfeng Wu

David J Sager

Koichi Yamada

Ron Gabor

Joseph Nuzman

Shlomo Raikin

Jamison D Collins

Tin-Fook Ngai

Ruchira Sasanka

Sebastian Winkel

Jayesh Iyer

Suresh Srinivas

Jayaram Bobba

Ho-Seop Kim

Omar M Shaikh

Leeor Peled

Jason A Domer

Jeffrey J Cook

Vineeth Mekkat

Girish Venkatasubramanian

Jeffery J Cook

A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

Instruction and logic for predication and implicit destination

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.

Methods and apparatus to optimize instructions for execution by a processor

Growing community of inventors

Sunnyvale, CA, United States of America

Howard Chen