International Business Machines Corporation

Howard Carl Tanner

Brian Michael Kerrigan

John Charlie Greek, Jr

Gary Dale Carpenter

Mark Edward Dean

Cuong T Nguyen

Marc Raymond Faucher

Michael Edward Criscolo

Gary Yuh Tsao

Binh Thai Hoang

James C Peterson

Stephen Sung

Timothy Michael Lambert

William Joseph Piazza

Sanjay Gupta

Robert Christopher Dixon

Walter S Rosenbaum

Jeffrey William Young

Jeffrey D Harper

Michael Eudell McBride

Sean Eugene Curry

Paul W Kalendra

Eric Sigfried Petterson

Anh Tran Vinh

Keith Andre Braithwaite

David Wesley Terry

A method in a data processing system for identifying a circuit. In a preferred embodiment, a set of bits, with a defined chain length, are shifted into the circuit one bit at a time. The bits shifted out from the circuit are compared to the bits, from the set of bits, shifted into the circuit to determine if the circuit corresponds to a first type circuit. The comparing step is accomplished before all bits in the set of bits have been shifted into the circuit. If the circuit is not a first type circuit corresponding to the set of bits shifted into the circuit, then the shifting of bits into the circuit is discontinued and the process is repeated with a second set of bits corresponding to a second circuit type until the circuit type has been identified.

Methodology for classifying an IC or CPU version type via JTAG scan chain

A system, device, and method for dynamically testing integrated circuits is disclosed. The system includes a first integrated circuit including input pins, output pins, normal operating logic, and control logic. The control logic is connectable to the input pins and configured to initiate a test interval based on a state of the input pins and to record the state of the input pins during the test interval. A second integrated circuit of the system includes input pins, output pins, normal operating logic, and test control logic. The control logic connectable to the output pins and configured to generate a user programmable set of test output signals. At least some of the output pins of the second integrated circuit are connected to at least some of the input pins of the first integrated circuit. The test control logic of the first integrated may be configured to initiate the test interval when the state of the input pins matches a predefined state. A portion of the test control logic of the first and second devices may be driven by a system clock that drives the operating logic such that the test output signals of the second device and the test input signals of the first device transition at the frequency of the system clock during the test interval. The test output signals may transition among one of a set of possible test output states, wherein the possible test output states include a predetermined pattern, an inverse of the predetermined pattern, an all 0's pattern, and an all 1's pattern.

Method and system for testing interconnected integrated circuits

A remote operator interface for a network computer is provided by a pocket-sized structural enclosure which remotely mounts input and output interface devices. The input and output devices providing a remote interface to control a network computer. The pocket-sized structural enclosure provides a means for electrically coupling the input and output interface devices to the network computer. The cable or data transmission medium which electronically couples the remote operator interface to the network computer provides a communication transmission medium for the network computer system. The pocket-sized structural enclosure can be mounted to a keyboard in close proximity to the operator of a network computer.

Remote operator interface for a network computer

A small network computer has a chassis which is mounted within a housing. A variety of electronic components are mounted to the chassis and a pair of feature card slots are located in a tailstock portion of the chassis. A full-sized 3.5 inch hard disk drive is mounted to a flat bracket in one of the feature card slots. The bracket inserts into the tailstock on one end and is fastened to the chassis on an opposite end.

Mechanical architecture of supporting a hard disk drive into a feature card slot in a network computer

A computer tower has a variety of electronic components mounted within an enclosure. Power and communication-type cables extend from the enclosure for connection to a power source and peripheral components such as a monitor or operator interface. A pedestal is mounted to the lower end of the enclosure to increase the stability of the computer tower when it is placed on a level surface. The bottom of the pedestal has a recess or channel which extends all the way around the pedestal near its outer edge. The unused length of the cables may be coiled into the channel of the pedestal for temporary and aesthetically appealing storage.

Cable storage compartment for network computer

A module type distinguishing apparatus and method for differentiating between modules based upon the presence or absence of a pulling resistor at a specified pin connection of the modules. A high impedance pulling resistance is connected to the line and is subject to sensing while a tri-state mode of operation is initiated in the module. The presence or absence of the pulling resistor in the module is detected and recorded in a register. Differentiation between module types is accomplished based upon the binary state of the data in the register. In a particularized implementation, industry standard L2 cache modules are distinguished as to tag bit size depending on the presence or absence of a pulling resistor as detected during tri-state operation of a tag output pin.

Connected module type distinguishing apparatus and method

A power supply interface suitable to provide voltages of appropriate magnitude to a static random access memory (SRAM) device from a combination of independent sources including a main power supply, an auxiliary power supply, and a battery. The voltages from the interface are at levels consistent with the SRAM modes of operation. During limited voltage tolerance read and write access operations, main power supply voltage is provided through a low forward voltage drop switched metal oxide field effect transistor (MOSFET). Parasitic paths, potentially producible by the transistor and affecting the battery source of power, are eliminated through the use of a second, complementary MOSFET. The second MOSFET is directly responsive to a POWERGOOD signal from the main power supply, indicating both an 'on' state and an appropriate voltage level of the main power supply.

Power supply interface circuit providing nonvolatile storage with

A system and method for protecting individual segments of a contiguous I/O address space on a system bus using the page access protection resources of a processor operating on a processor bus address space. The contiguous I/O address space is segmented and mapped by translation into the processor address space by distributing I/O segments non-contiguously among successive processor bus pages. Individual I/O address space segments, as may be associated with I/O ports, are protected directly by the processor through the selective enablement of page protection for correspondingly mapped ports.

Non-contiguous mapping of I/O addresses to use page protection of a

A register distributed across multiple single port adapters allows the system to operate the single port adapters identically to a single multi-port adapter. Each adapter has its own priority logic identical to the logic used on a multi-port adapter to select an individual port. The priority logic on the adapter allows the system to deselect one adapter and select another adapter in one operation. Each adapter has switch settings to allow selective control of individual bits on the system bus, which allows multiple adapters to respond to the processor simultaneously for different ports in the same manner as a multi-port adapter. By replying simultaneously, the system can use the same software to control two different hardware adapter types: single port, or multi-port.

Apparatus and method for addressing multiple adapter cards in one

A system and method for connecting a short word length memory to a significantly wider bus operated in an address/data multiplexing mode. A mode of operation is defined for the bus whereby the bus lines are divided for purposes of memory accessing into a data group and an address group. The data group is operable bidirectionally to read or write memory, using the addresses provided on the group of address lines. This architecture and practice is particularly suited for a boot ROM used with processors, in that such ROMs are normally of relatively short word length while the processors are of relatively long word length and are accordingly connected to buses of similar long word length. Bridge logic interfaces the processor bus to the ROM for sequencing, timing and supplemental control in converting the data from the ROM format to the processor format.

Connecting a short word length non-volatile memory to a long word length

Improved hyphenation apparatus is combined with word verification apparatus to automatically provide hyphenation points for input words from a keyboard or other input device. The spelling of each word input to the system is verified by the digital reference matrix section of the apparatus by calculating a vector magnitude and angle for the word which is compared to the contents of a storage dictionary of words. Each cell of storage in the storage dictionary, in addition to containing a unique angle representation of the input word, contains a byte of data representing the valid hyphenation points for the input word. When an input word is verified to be correctly spelled, the hyphenation byte is read out of dictionary and used by the hyphenation section to reassemble the word in hyphenated form. The hyphenated word is then displayed to the operator for appropriate action.

Apparatus for automatically forming hyphenated words

A system which utilizes a floating hot zone for controlling quality of ultimately justified output text. In preparing text for later justified output, the minimum space size is set at three units. The zone is variable in width and located within the measure and adjacent the right margin. The width of the zone is partially dependent upon the number of spaces on a line. During printing, the left side of the zone is tentatively established when the residue is equal to, or less than, 36 units. Then, when the residue is equal to, or less than, the number of spaces times nine, the system will cause a bell to ring. This will alert the operator that the zone has been entered and if printing is thereafter terminated, the maximum space size will not exceed 12 units during later justified output.

Indicating entry into a variable width right margin zone

A system for positioning final copy printed text, upon a first printing, at a specified location on a line in a format determined by input keying. The location can be a blank block on a form to be filled in. After initial setup and during any input or output operation, a final copy printed text mode can be entered by an operator and stored. This will inhibit printing upon further keying until a carrier return is keyed following the text. The printer carrier is positioned through spacing, backspacing, tabbing, etc. relative to the left side of the block, and codes representative thereof are also stored. When the carrier is at the left side of the block, the keying of a variable space or character will define a tentative format and this location, and a variable space or character code will be stored. Then the text is keyed and stored. After the text has been keyed, the keying of spaces, backspaces, tabs, and/or variable spaces will result in codes representative thereof being stored and the final copy text format being finalized. When the carrier is located at the right side of the block, a carrier return is keyed and this location is defined by the storing of a segment end code. The carrier is then automatically returned to the position occupied at the time of keying the final copy printed text mode. Thereafter, the carrier is positioned at the beginning print point for the format determined by input keying, and the final copy text is printed.

Format control system for positioning final copy printed text

A system for printing a plurality of sequentially stored text columns in a side-by-side format. Corresponding lines from each column are printed out on a print line in operator defined locations. After a line from one of the columns is printed on a print line, the carrier caused to escape, and any corresponding lines from succeeding columns are printed on the same line prior to causing a printer carrier return.

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Austin, TX, United States of America

Howard Carl Tanner