Bell Telephone Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

At&t Bell Laboratories

Mostek Corporation

Thomson Components-mostek Corporation

Howard C Kirsch

James H Stefany

Frank J Procyk

David Beecham

James T Nelson

Clinton H Holder, Jr

Glen T Cheney

A self-aligned one transistor-capacitor memory cell is provided which uses an n-channel MOS transistor having separate drain and source regions with a first level polysilicon conductor coupled to the top plate of the capacitor and separate second level polysilicon conductors coupled to the gate and drain of the transistor. A reduction in a dimension of the memory cell is acheived compared to a similar memory cell which uses only one level of conductors.

Dual level polysilicon single transistor-capacitor memory array

As integrated field effect devices are scaled to smaller dimensions, the electric field in the channel increases for a constant operating voltage. This induces 'hot electron' effects that reduce device reliability. The present invention reduces the voltage (and hence electric field) across one or more transistors in various complementary (e.g. CMOS) logic circuits. This is achieved while still obtaining a full logic swing (e.g., 0-5 volts) at the output of the logic. The technique also allows the retention of previous voltage levels (e.g., 5 volts) for operation of other portions of the integrated circuit (e.g., dynamic memory cells).

IGFET gating circuit having reduced electric field degradation

A dynamic memory obtains reduced leakage currents through the access transistors by preventing the low-going column conductors from reaching zero volts for at least a majority of the duration of the active portion of a memory cycle. The low-going conductors are allowed to reach zero volts during the refresh operation. One advantage is a possible increase in the data storage time between required refresh operations. An increase in the refresh interval is especially useful for memory operations wherein a multiplicity of columns are selected for a given row selection. The present technique also addresses the tendency toward increased sub-threshold leakage as field effect transistor thresholds decrease.

Dynamic memory with increased data retention time

A TTL to CMOS input buffer (20) which prevents static current flow when the TTL input signal is at a relatively low voltage logic '1' state. A transition detector (44) responsive to the input TTL logic signal and a voltage boosting circuit (50) connected between a positive power supply (VDD) and the input to a first CMOS inverter (30) are utilized to sense an input signal '0' to '1' transition and boost the TTL logic '1' signal to a voltage level which will prevent the p-channel transistor (32) included in the CMOS inverter from turning 'on'. The voltage boosting circuit will subsequently be disconnected from the input to the p-channel transistor to prevent the input from being fully charged to the positive power supply.

Zero standby current TTL to CMOS input buffer

A single ended sense amplifier (10) receives a bit line signal (16) at the gate of a detector MOS transistor (36). The source of the detector transistor (36) is connected to a reference voltage (24) which is adjusted prior to each memory cycle to make the gate to source voltage of the detector transistor (36) equal to the approximate threshold voltage of the transistor. The drain of the detector transistor (36) gates an amplifier transistor (30) which inhibits or passes a read signal (18) to the gate of a digit line pull down transistor (32) which provides an active pull down on a digit line (26) that is precharged to a high voltage prior to a memory read cycle.

Sense amplifier for a dynamic RAM

A dynamic random access memory obtains improved access time for reading data from a multiplicity of memory cells along a given selected row. This is obtained by allowing the output data line to remain active between activations of a column enable signal. An increase in data valid time at the memory output is obtained, while allowing increased latitude in memory address setup time.

Fast column access memory

A dynamic random access memory has a row conductor boosted in excess of the power supply level during an initial portion of a memory cycle. The voltage is then clamped at the supply level during the middle portion of the cycle, and optionally boosted again during the refresh portion. This allows improved performance and reliability, especially in memories employing bit lines precharged to one-half the power supply level.

Semiconductor memory with boosted word line

An integrated circuit comprises a node that is boosted by one or more boost capacitors depending on the level of the power supply voltage. When the level is below a given threshold, a first booster capacitor is activated. Additional boost capacitors may be provided for activation at still lower thresholds. The boost capacitors are deactivated when the power supply level exceeds the corresponding thresholds. In this manner, a more constant boosted voltage is obtained. This provides for an adequate boosted voltage at low power supply levels, while avoiding excessive boost at high power supply voltages that could damage devices. The technique may be used for boosted row conductors in dynamic random access memories, among other applications.

Integrated circuit having a variably boosted node

A clock generator circuit (10) receives an input signal PPC.0. and generates a delayed clock output signal PC.0.. The circuit (10) is set to an initial condition by a precharge signal PC.0.R prior to a transition of the input signal PPC.0.. A time delay signal is produced at a node (26) by operation of transistors (18, 28). The transition of the input signal PPC.0. produces a bootstrapped voltage at a capacitor (68). The delay signal activates a transistor (80) to couple the bootstrapped voltage to the gate terminal of an output transistor (88). The gate terminal of the output transistor (88) is driven directly from a low voltage state to a boosted high voltage state. This causes the output signal PC.0. to be driven from an initial low voltage state to the power supply voltage V.sub.cc without intervening steps. The output transistors (88, 90) of circuit (10) are never activated at the same time, thereby preventing any current spike from being propagated through the circuit (10).

Bootstrapped clock driver including delay means

A buffer circuit (10) receives a TTL input signal at an input node (12) and produces an MOS logic signal at an output node (38). A capacitor (22) is precharged by a precharge signal (PC) to a high voltage state and a control node (32) is precharged to a high voltage state. An input transistor (14) receives a reference voltage which is a function of the levels of the TTL input. When the TTL input is high the transistor (14) is nonconductive thereby maintaining the charge at the control node (32) to render conductive a pull-down transistor (36) which drives the output signal at the output node (38) to a low state. When the TTL input signal goes to a low voltage state the input transistor (14) is rendered conductive by discharging a terminal of the capacitor (22). A second terminal of the capacitor (22) is driven to a lower voltage state to render conductive a discharge transistor (30) which connects the control node (32) to the node ( 24) connected to capacitor (22). This serves to discharge the control node (32) thereby turning off the pull-down transistor (36) and permitting a pull-up transistor (40) to drive the output node (38) to a high voltage state. The buffer circuit (10) functions as an inverter and provides a rapid transition of the output signal in response to a transition of the input signal.

MOS Bootstrapped buffer for voltage level conversion with fast output

A delay gate circuit consists of first and second stages which each have two serially connected MOS transistors and of a fifth MOS transistor. The gates of the transistors of the first stage serve as first and second circuit input terminals. The gate of the second transistor of the first stage is connected to the gate of the first transistor of the second stage. An output terminal of the first stage is connected to the gate of the second transistor of the second stage and to the drain of the fifth MOS transistor. An output terminal of the second stage is connected to the gate of the fifth transistor and serves as the output circuit terminal.

Delay gate circuit

Voltage generator circuitry uses a first capacitor (Q1) that is selectively isolated from an output terminal (26) by a first transistor (Q4). The gate of Q4 is coupled to a circuit terminal (16) which is capacitively coupled via second capacitor (Q5) to the output terminal (20) of a delay gate (28). The first capacitor (Q1) is charged to a potential level near or at that of a power supply (VDD) and then a positive going waveform applied to Q1 causes it to be charged to a potential level above VDD. Terminal 16 is charged by the positive going waveform to a value at or near VDD and then it is increased in potential after the delay time of the delay gate (28). This enables (biases on) Q4 and allows the output terminal (26) to assume a potential level greater than that of VDD.

Voltage generator circuitry

A dynamic sense-refresh detector amplifier consists essentially of a cross coupled MOS transistor pair and two sets of load-refresh circuits which each include a capacitor and three MOS transistors. The load-refresh circuits eliminate the negative effect of threshold voltage losses on noise margin by allowing the memory cell from which information is read out and sensed to be refreshed to full 1 and 0 levels. A control terminal of a transistor of each load-refresh circuit is coupled to the transistor of cross coupled pair not associated with that load-refresh circuit. In addition, a voltage clamping transistor is used with each load device to further increase operating noise margins. The dynamic operation of the amplifier allows for relatively low power dissipation.

Dynamic sense-refresh detector amplifier

The current in a semiconductive light emitting diode (LED), driven by an insulated gate field effect transistor (IGFET) switch, is stabilized by a current control circuit including a comparator type feedback network, which stabilizes the voltage at a node located between said switch and the series connection of a ballast resistor and the LED.

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Emmaus, PA, United States of America

Howard C Kirsch