Motorola Corporation

Anadigm Limited

Howard C Anderson

Danny A Bersch

David J Anderson

Doug Garrity

Brad D Gunter

Ian Craig Macbeth

Timothy James Streit

Cezary Antoni Marcjan

William M Peterson

Robert H Leivian

Sidney C Garrison

Dennis Wodarz

Troy Franklin Giles

Brian Eugene Nottingham

Christopher Robin Schene

A system is provided for programming a configurable semiconductor device. The system includes a programmable controlling device, a programmable computing device, a communication link, a configurable hardware device, a design tool with first computer program code, and second computer program code. The configurable hardware device has memory with a plurality of memory locations and coupled with the programmable controlling device via the communication link. The design tool includes first computer program code embodied in a programmable computing device. The second computer program code is generated at least in part by the first computer program code and is embodied in the programmable controlling device for: a) applying configuration data to selected memory locations within the configurable hardware device to configure the configurable hardware device; b) determining a location of a subset of at least one of (i) the programmable memory locations in the configurable hardware device and (ii) the configuration data to be modified; and c) determining a new data value to be applied to the subset of at least one of (i) the memory locations in the configurable hardware device and (ii) the configuration data. The design tool provides at least one of configuration data, address data, and a data value algorithm usable in performing at least one of a), b), and c). A method is also provided.

System and method for configuring analog elements in a configurable hardware device

An apparatus is provided for programming a programmable circuit device capable of realizing at least one sub-circuit by wiring together at least one circuit component. The programmable circuit device includes a programmable computing device, a user interface, and a design tool. The user interface is associated with the programmable computing device. The design tool is associated with the programmable computing device and is configured for interaction with a user at the user interface. The design tool includes computer program code embodied in the programmable computing device including a sub-circuit definition containing information for defining at least one of multiple configurations, topologies, and parameters of a sub-circuit of a programmable device. A method is also provided.

Apparatus for programming a programmable device, and method

A method is provided for configuring a programmable semiconductor device. The method includes using the configuration data of a macro (,A) or a plurality of macros to configure the programmable semiconductor device. The configuration data of the macro (,A) is combined with the configuration data of a work area (,). The programmable semiconductor device is configured using the combined configuration data of the macro (,A) and the work area (,).

Method for configuring a programmable semiconductor device

A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

Circuits and method for reducing voltage error when charging and

A circuit and method for reducing voltage error when charging and discharging a variable capacitor (44) through a switch (43). The switch (43) comprises a plurality of transmission gates (53-55) coupled in parallel. A control circuit (42) provides control signals for enabling transmission gates of the plurality of transmission gates (53-55). The control circuit (42) changes the resistance of the switch (43) by selecting an appropriate transmission gate wherein each transmission gate has a different resistance. The resistance of the switch (43) is varied as a capacitance of the variable capacitor (44) is changed to maintain a predetermined RC time constant over the entire range of capacitor values of the variable capacitor (44).

Circuit and method for reducing voltage error when charging and

A method is provided for using a scroll bar to select and view exact pages of a document without downloading unwanted pages of the document. Instead of displaying all the pages before a particular page is selected via scroll bar, the method does not display any of the incremental or unwanted pages before the actual selected page is selected, retrieved and displayed.

Resolution compensating scroll bar valuator

An artificial neural network is provided using a modular, self-organizing approach wherein a separate neural field is contained within each module for recognition and synthesis of particular characteristics of respective input and output signals thereby allowing several of these modules to be interconnected to perform a variety of operations. The first output and second input of one module is respectively coupled to the first input and second output of a second module allowing each module to perform a bi-directional transformation of the information content of the first and second input signals for creating first and second output signals having different levels of information content with respect thereto. In the upward direction, the first low-level input signal of each module is systematically delayed to create a temporal spatial vector from which a lower frequency, high-level first output signal is provided symbolic of the incoming information content. Since the first output signal contains the same relevant information as the first input signal while operating at a lower frequency, the information content of the latter is said to be compressed into a first high-level output signal. In the downward direction, a second output signal having a low-level of information content is synthesized from a second input signal having a high-level of information content. The second input signal is the best prediction of the first output signal available from the knowledge base of the module, while similarly the second output signal is the prediction of the first input signal.

SPANN: Sequence processing artificial neural network

A resistive network is responsive to a spatial vector formed by sampling an input signal for providing the simultaneous complex transformation thereof at a plurality of outputs. A matrix representation of the sum of products estimation of the complex transform provides the connection scheme and the individual values for the resistors comprising the resistive network. These resistors are interconnected in a meshwork of first and second conductors with a predetermined correspondence between the resistor network and the elements of the matrix of the sum of products estimation. Inverters are coupled to predetermined ones of the plurality of first conductors for inverting the polarity of predetermined elements of the spatial vector of the input signal wherein the predetermined ones of said plurality of first conductors are identified from the matrix of the sum of products estimation. In the transformation, the spatial vector of the input signal is applied to the plurality of first conductors. The predetermined connection scheme and the predetermined values of the resistive network converts the spatial vector of the input signal to a plurality of signals flowing through the plurality of second conductors for providing a spatial vector output signal proportional to the complex transformation of the input signal.

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Tempe, AZ, United States of America

Howard C Anderson