Philips Electronics North America Corporation

Other

Howard B Pein

Stephen L Wong

Michael Bakhmutsky

Wen-Jian Gu

Viktor L Gornstein

Gregory T DiVincenzo

Paulo Caldiera

A high speed variable length decoder with an enhanced architecture for minimizing the propagation delays within the processing paths of the variable length decoder. The variable length decoder includes an input circuit for receiving code words and outputting a sequence of bits on a corresponding sequence of parallel lines that define a decoding window. The input circuit preferably includes a 'one-hot' bit stream barrel shifter matrix having a shift input. The decoding window is input to a 'one-hot' word length decoder that provides a numbered sequence of output lines. The 'one-hot' word length output of the 'one-hot' word length decoder is applied to an input of a 'one-hot' ring barrel shifter matrix, and an input of a 'one-hot' overflow barrel shifter matrix. The output of the 'one-hot' ring barrel shifter matrix is a 'one-hot' word pointer which shifts the decoding window to the next code word to be decoded. This enhanced 'one-hot' architecture greatly accelerates the word length computation loop of the variable length decoder of the present invention relative to the presently available variable length decoders having a conventional architecture. The decoding window is also connected to the input of a code word value decoder circuit. The code word value decoder circuit determines the values of code words and provides the decoded values at the output of the variable length decoder. A control circuit controls the operation of the value decoding circuit, the word length computation loop, and the input circuit, in accordance with a prescribed decoding protocol, e.g., an MPEG protocol.

Variable length decoder with one of N length indicator

Digital processing of current signals allows close matching of arbitrary time delay curves for a circuit breaker. An analog signal proportional to the current is sampled and digitized. Digital samples, with or without further processing, are used to select increment values from a look-up table for accumulation in a counter. The counter is decremented periodically to simulate cooling of the circuit being protected. The values in the look-up table are determined according to the desired time delay curve. Processing of the digital samples may include squaring samples, accumulating the squared values to form a subtotal which is compared with an instantaneous trip threshold, accumulating the subtotals for a time period equal to half a cycle of AC line voltage, taking the square root of the accumulated subtotals, and using that square root as the address for looking up the increment value.

Electronic processing unit, and circuit breaker including such a unit

A non-volatile memory cell and array of such cells is provided. The memory cell includes a single transistor floating gate cell fabricated on a sidewall of a silicon pillar etched into a silicon substrate. The memory cells are arranged in an array of rows extending in a bit line direction and columns extending in a word line direction. A substantially smaller cell and array size is realized by limiting the dimension of the pillar and the bit line in the word line direction to be the minimum line width as limited by the lithography.

Method of fabricating non-volatile sidewall memory cell

Non-volatile sidewall memory cell method of fabricating same

A lateral Semiconductor-On-Insulator (SOI) device includes a substrate, a buried insulating layer on the substrate, and a lateral semiconductor device such as an LDMOS transistor, an LIGBT or a lateral thyristor on the insulating layer. The semiconductor device (in the case of an LDMOS transistor) includes a source region, a channel region, an insulated gate electrode over the channel region, a lateral drift region formed of a continuous layer of a lightly-doped semiconductor material on the buried insulating layer, and a drain contact region which is laterally spaced apart from the channel region and connected to the channel region by the drift region. A buried diode is formed in the substrate, and is electrically coupled to the drain contact region by a portion of the drift region which extends laterally in the region between the drain contact region and the buried diode.

Lateral semiconductor-on-insulator (SOI) semiconductor device having a

A lateral Semiconductor-On-Insulator (SOI) device includes a substrate, a buried insulating layer on the substrate, and a lateral semiconductor device such as an LDMOS transistor, an LIGBT, a lateral thyristor, or a lateral high-voltage diode on the insulating layer. The semiconductor device (in the case of an LDMOS transistor) includes a source region, a channel region, an insulated gate electrode over the channel region, a lateral drift region on the buried insulating layer and having a substantially linearly graded lateral doping profile, and a drain region which is laterally spaced apart from the channel region and connected to the channel region by the drift region. In order to substantially improve the breakdown voltage of the device, typically a high-voltage power device, while reducing the 'on' resistance, the lateral drift region is formed of a wide bandgap semiconductor material such as silicon carbide.

Growing community of inventors

Briarcliff Manor, NY, United States of America

Howard B Pein