Broadcom Corporation

Entropic Communications, Inc.

Western Digital Technologies, Inc.

Western Digital Corporation

Mobius Semiconductor, Inc.

Howard A Baumer

Aaron W Buchwald

Hui Wang

Xicheng Jiang

Avanindra Madisetti

Michael Q Le

Vasudevan Parthasarathy

Abbas Amirichimeh

Linda Ying

Martin Lund

Jurgen Van Engelen

John Louie

Wael William Diab

Ali Ghiasi

Myles H Wakayama

Josephus A Van Engelen

Hoang Tan Tran

Chung-Jue Chen

Gary S Huff

Rajesh Satapathy

Jay Proano

Hairong Yu

Dwight Oda

Pieter Vorenkamp

Scott R Powell

Patricia Ann Thaler

Howard M Frazier

Maurice David Caldwell

Scott Sterling McDaniel

Robert L Cloke

Peiqing Wang

Patrick J Lee

Vivek Telang

Magesh Valliappan

Gerald W Shearer

Jatan Shah

Josephus Van Engelen

David Kyong-sik Chung

Anthony Brewster

Scott Mcdaniel

Methods and systems for a digitally controlled oscillator may comprise, for example, an all-digital all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising a thermometer pulse coder comprising a plurality of frequency control word signal lines. the thermometer pulse coder may be configured to generate a frequency control word from a binary encoded frequency control word, where the frequency control word may comprise hermometer coded signals and a pulse modulated dither signal, and may select a frequency control word signal line over which to transmit the pulse modulated dither signal and may transmit the thermometer coded signals over another of frequency control word signal lines. A digitally controlled oscillator may be configured to receive a frequency control word and generate an output clock signal at a frequency determined using at least the frequency control word.

Digitally controlled oscillator

A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal. The method to provide a multi-rate Physical layer (PHY) interface comprises receiving a select signal from a Physical layer (PHY) layer indicating data rate of a first set of signals, selecting a first interface and turning off the second interface if the select signal indicates the first interface is to be used, selecting the second interface and turning off the first interface if the select signal indicates the second interface is to be used and transmitting the first set of signals using the second interface or a subset of the first set of signals using the first interface based on the select signal.

Multi-rate MAC to PHY interface

A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port SERDES transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a 'ring' structure (or donut 'structure') around the logic core, and is configured between the logic core and the data ports.

Multi-rate, multi-port, gigabit SERDES transceiver

Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.

Digitally controlled oscillator with thermometer sigma delta encoded frequency control word

Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard. In addition, the multilane to single lane digital interface translator is configured to decode the received data into data streams, and interleave the data streams to form packets, the multilane to single lane digital interface translator is configured to insert auxiliary data received via the auxiliary channel input and idle data between the packets to produce an output data stream that is rate matched to the second data rate, and the multilane to single lane digital interface translator is configured to encode the output data stream in accordance with the output digital interface standard.

Systems and methods for digital interface translation

Systems and methods for transmitting data having a rate indicated by an associated clock signal, using a fixed rate transmission system are disclosed. One embodiment of the invention includes an unknown rate to fixed rate transmitter configured to receive unknown rate data and a clock signal that indicates the rate of the unknown rate data, and to transmit data at a fixed rate over a fixed rate link, a fixed rate to unknown rate receiver configured to receive fixed rate data including the unknown rate data via the fixed rate link, and to transmit the unknown rate data, and a recovered clock signal. In addition, the unknown rate to fixed rate transmitter is configured to insert idle data between the fixed rate data so that transmitting the combined unknown rate and idle data at the fixed rate over the fixed rate link results in the unknown rate data being transmitted over the fixed rate link at a rate corresponding to the rate indicated by the clock signal, and the fixed rate to unknown rate receiver is configured to accumulate the unknown rate data and generate a recovered clock signal based upon the rate at which the unknown rate data is accumulated by the fixed rate to unknown rate receiver.

Unknown rate clock recovery from fixed rate transmission system

Methods and systems adaptively equalizing an analog information signal, the method including sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples, and equalizing the analog samples to produce equalized analog samples. The equalizing includes determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples, and adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude.

Methods and systems for adaptive receiver equalization

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

High-speed serial data transceiver and related methods

A system and method for energy savings on a PHY/MAC interface for energy efficient Ethernet. Power savings for a PHY due to low-link utilization can also be realized in the higher layer elements that interface with the PHY. In one embodiment, subrating is implemented on a MAC/PHY interface to match a subrating of the PHY with a remote link partner. This subrating is less than the full capacity rate and can be zero.

System and method for energy savings on a PHY/MAC interface for energy efficient Ethernet

A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase

Aspects of a method and system for physical layer aggregation are provided. An example method includes receiving, form a medium access control (MAC) layer protocol entity, data encapsulated into a packet comprising a preamble, fragmenting said packet into a plurality of fragment payloads, and conveying each of said fragment payloads to said third portion of said one or more circuits, wherein at least one of said plurality of fragment payloads comprises one or more octets copied from said preamble.

Method and system for physical layer aggregation

Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.

A system and method for using sequence ordered sets for energy efficient Ethernet communication. Sequence ordered sets can be generated by a first device for communication of parameter(s) to a second device, which parameters can be used in implementing an energy efficient Ethernet control policy. Sequence ordered sets can be used in communication between physical layer devices, or between a physical layer device and a media access control device. In one example, the sequence ordered set can identify a point at which a rate transition is to occur.

System and method for using sequence ordered sets for energy efficient Ethernet communication

Growing community of inventors

Laguna Hills, CA, United States of America

Howard A Baumer