Semiconductor Components Industries, LLC

How Kiat Liew

Sw Wang

Ch Chew

Soon Wei Wang

Shutesh Krishnan

Fui Fui Tan

Eiji Kurose

Francis J Carney

Chee Hiong Chew

Bih Wen Fon

Jose Felixminia Palagud, Jr

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Thin semiconductor package for notched semiconductor die

Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

Molded semiconductor package and related methods

Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

Quad flat no leads package with locking feature

Thin semiconductor package and related methods

A chip package, in some embodiments, comprises: a die flag; one or more die supports; and a die mounted on the die flag and on said one or more die supports, at least one surface of said die having an area larger than an area of at least one surface of the die flag.

Die support for enlarging die size

A chip scale package (CSP) includes a die and a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead. The first surface of the first lead forms a first plane. A second lead is mechanically coupled to a second surface of the die at a first surface of the second lead. The first surface of the second lead forms a second plane. A mold compound at least partially encapsulates the die, forming a CSP. The first plane and the second plane are oriented substantially perpendicularly to a third plane formed by a motherboard surface when the CSP is coupled to the motherboard surface. The CSP includes no wirebonds and the first lead and second lead are on opposing surfaces of the CSP. The third plane of the motherboard may be a largest planar surface of the motherboard.

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Bukit Jalil, Malaysia

How Kiat Liew