Credence Systems Corporation

Synopsys, Inc.

Heuristic Physics Laboratories

Heuristics Physics Laboratories, Inc.

Hovhannes Ghukasyan

Yervant D Lepejian

Lawrence A Kraus

Hrant Marandjian

John M Caywood

Arman Sagatelian

Suren Chilingaryan

Gurgen Lachinian

A dynamic database management system includes a data dictionary, a data importer and a query front-end. The data importer automatically imports data from an input file into a database, while adding new tables for new attributes as necessary, and updating parameters and folders tables in the data dictionary accordingly, so that end-users may access the imported data by database queries through the query front-end.

Dynamic database management system and method

A method is described for automatic generation of join graphs for relational database queries. The method includes marking instances of tables in a hierarchical representation of a database schema according to a selection procedure that processes tables in an input list having single occurrences in the hierarchical representation, multi-dimensional tables in the input list having multiple occurrences in the hierarchical representation, one-dimensional tables in the input list having multiple occurrences in the hierarchical representation that reference the multi-dimensional tables and have one of the multi-dimensional tables as a parent in the hierarchical representation, and any remaining one-dimensional tables in the input list having multiple occurrences in the hierarchical representation. The hierarchical representation is configured using expert knowledge of the database usage.

Automatic generation of join graphs for relational database queries

A software development tool employing workflows for developing user interactive programs is described. The tool includes means for displaying a workspace on a computer screen, and means for displaying objects on the computer screen that are individually selectable to be placed and coupled together in the workspace to define a workflow for a user interactive program. Several objects have interactively alterable operation parameters. One object performs an interactively alterable switch function for directing data flow within the workflow. Another object facilitates branch processing according to a user indicated selection from displayed information generated by the user interactive program. Another object facilitates assigning a name to an input port of another object so that data may be directly provided to that input port. Another object prompts a user for input when a condition is met while executing the user interactive program. Also described is a method performing these functions of the software development tool.

Software development tool employing workflows for developing user interactive programs

A BIST function is provided in which both the routing area devoted to the test signals and the area devoted to the circuits required to implement the BIST routines are minimized, while also including the ability to test a plurality of embedded memories at full speed in parallel. Testing the memories at full speed both reduces test time and improves the quality of the testing.

Method and apparatus for built-in self test of integrated circuits

A BIST function is provided in which both the row address and the column address of a memory to be tested may be selected independently. The present invention provides flexibility in selecting addresses to be tested, improves transition time between rows, and allows determination of which memory address passes or fails the test.

A method and apparatus are provided for automatically generating the design of a BIST for embedded memories of an IC. The approach relies on counters or pseudo-random generators for the implementation of many of the functions. The invention incorporates software that generates equations that can be used as inputs to a logic synthesis tool. The output of the synthesis tool feeds an automatic routing tool where it is merged with the output of the synthesis of the other portions of the integrated circuit, IC. The routing tool places and routes the signals through the logic described by the synthesis tool along with the remainder of the IC. The result is a completed IC design that includes efficient memory BIST circuitry.

Automatic generation of user definable memory BIST circuitry

A built-in self test (BIST) circuit for an integrated circuit tests one or more embedded memories by writing data to each memory address, reading it back out, and then comparing the input and output data to see if they match. The BIST circuit includes one or more data generators for supplying a sequence of data to be written to the various addresses of each memory and one or more identical address generators, each for supplying addresses to a separate embedded memory during read and write operations. Though the memories may have differently sized address spaces, all address generators generate a similar address sequence having a range of address values as large or larger than the address space of the largest memory. During each memory write cycle, a separate filter checks the address output of each address generator to determine whether the address is within the address space of the corresponding memory. If so, the BIST circuit writes the current data output of a data generator to that address of the memory. If not, the BIST circuit ignores the current address and data outputs of the address and data generators and repeats the write operation it performed during a next preceding memory write cycle, writing the same data to the same valid memory address. The BIST circuit makes a similar address substitution during write operation. This allows the BIST circuit to use identical address generators for all memories regardless of the size of the memory being tested.

Efficient built-in self test for embedded memories with differing

A method and circuit are provided for generating a minimum-sized address filter to detect when the address space of an embedded memory having a smaller address space than another larger embedded memory is being exceeded. The method includes decomposing a maximum address into alternating sequences of consecutive binary ones (1's) and zeros (0's), discarding a final sequence if it contains binary 1's, and generating a filter circuit from a filter function formed from the alternating sequences of consecutive binary 1's and 0's. A built-in self test (BIST) circuit incorporating the address filter provides the ability to test a plurality of embedded memories at full speed in parallel. A computer system including a computer program for generating the filter circuit may also be provided.

Growing community of inventors

Yerevan, Armenia

Hovhannes Ghukasyan