Google Inc.

Houle Gan

Mikhail Popovich

Yujeong Shim

Chenhao Nan

Woon-Seong Kwon

Xin Li

Teckgyu Kang

Shuai Jiang

Gregory Sizikov

Qiong Wang

Namhoon Kim

William F Edwards

Chee Yee Chung

Thomas James Norrie

Runruo Chen

Ryohei Urata

Nam Hoon Kim

Melanie Beauchemin

Georgios K Konstadinidis

Kaushik Vaidyanathan

Woon Seong Kwon

Richard Roy

Xu Zuo

Binayak Roy

Robert Ashby Armistead, Iii

Shinnosuke Yamamoto

Cheng Chung Yang

A method includes forming a module aperture in a printed circuit board assembly ('PCBA'), forming an electronic communication interface extending around the module aperture, and plugging a pluggable processor module into the module aperture, the pluggable processor module comprising a micro-processor package, a voltage regulator, and a contact. An electronic communication interface of the pluggable processor module is placed in contact with the electronic communication interface of the PCBA.

Method of plugging a pluggable processor into a PCBA

A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.

Trans-inductor voltage regulator for high bandwidth power delivery

The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Backside integrated voltage regulator for integrated circuits

The subject matter described herein provides systems and techniques for the integration of TLVR technology in a vertical power VR module. A multiple-secondary TLVR topology using a controlled leakage inductance in the place of a separate compensation inductor, Lc, may be employed for the vertical power VR module. In addition, the capacitance inside the device to which the TLVR based vertical power VR module supplies power, rather than an output capacitance board, may be used in order to allow the module to be a single layer. Example structures that may include one or more primary windings and/or one or more secondary windings for each of possibly multiple linked phases of the TLVR based module are provided. The windings may be formed using traditional copper windings or printed circuit board (PCB) copper trace winding.

Integrating trans-inductor voltage regulator (TLVR) in vertical power delivery

Controlling voltage supplied to a load includes predicting a load current transient, generating a turbo signal in response to predicting the load current transient, and increasing, in response to the turbo signal, responsiveness of a voltage regulator supplying voltage to the load.

Predictive load transient based voltage regulator turbo for voltage droop minimization

An assembly includes a printed circuit board ('PCB'). An aperture extends through the PCB. The assembly also includes an array of pins and a processor package. The array of pins extends around a perimeter of the aperture, and the processor package extends over the aperture. The processor package is pressed against the array of pins by a compressive force couple.

Structure for optimal XPU socket compression

A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contacts that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board. An assembly includes the pluggable processor module and a printed circuit board assembly ('PCBA') including a module aperture that is large enough to receive the power board and narrower than the capacitor board.

Pluggable CPU modules with vertical power

The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.

Power modules with elevated inductors and capacitors arranged under the inductors

A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.

Power throttling mechanism using instruction rate limiting in high power machine-learning ASICs

An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Power sequencing in an active silicon interposer

A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.

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Santa Clara, CA, United States of America

Houle Gan