Taiwan Semiconductor Manufacturing Comp. Ltd.

National Applied Research Laboratories

Hou-Yu Chen

Kuan-Lun Cheng

Ching-Wei Tsai

Yu-Xuan Huang

Shyh-Horng Yang

Cheng-Ting Chung

Yong-Yan Lu

Yi-Bo Liao

Chih-Wei Kuo

Yuan-Shun Chao

Chun-Feng Nieh

Yu-Chang Lin

Chia-Wei Soong

Chih-Hao Wang

Huicheng Chang

Chih-Pin Tsao

Chi-Yi Chuang

Fu-Liang Yang

Chenming Hu

Kuo-Nan Yang

Kuan-lun Cheng

Chun-Fu Cheng

Wei Ju Lee

Wang-Chun Huang

Wen-Tai Lu

Chih-Kuan Yu

Chung-Pin Huang

Chuan-Li Chen

Yao-Ling Huang

Ming-Hua Yu

Chung-Hui Chen

Pei-Yu Wang

Donald Y Chao

Chen Hua Tsai

You-Lin Chu

Sai-Hooi Yeong

Kuo-Cheng Chiang

Jiann-Tyng Tzeng

Tzu-Chiang Chen

Chao-Ching Cheng

I-Sheng Chen

Mao-Lin Huang

Jia-Ni Yu

Chung-Wei Hsu

Lung-Kun Chu

Yu-Lin Yang

Chao-Hsuing Chen

Chie-Iuan Lin

Yi-Ling Chan

Min-Cheng Chen

Chia-Yi Lin

Yu-Sheng Wu

Yonag-Yan Lu

Kuo Lung Li

Yi-Lang Chen

Wei-Cheng Lin

Shih-Wei Peng

Huan-Chieh Su

Zhi-Chang Lin

Chun-Yuan Chen

Li-Ting Wang

Yi-Hsun Chiu

Te-Hsin Chiu

Wei-An Lai

Jin Cai

Ming Chian Tsai

Yi-Ling Chang

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes semiconductor material layers stacked above a substrate along a first direction and a gate structure wrapping around the semiconductor material layers. The semiconductor structure further includes an epitaxial structure coupled to the semiconductor material layers in a second direction that is different from the first direction and a SiGe-containing layer located below the epitaxial structure. In addition, a material of the SiGe-containing layer is different from a material of the epitaxial structure, the SiGe-containing layer comprises a first portion with a first thickness in the first direction, and a second portion with a second thickness in the first direction, and the second thickness is smaller than the first thickness.

Gate-all around transistor with isolating feature under source/drain

A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.

Field effect transistor with air spacer and method

An integrated circuit (IC) device includes a first plurality of active areas extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and a second plurality of active areas extending in the first direction, offset from the first plurality of active areas in the first direction, and having a second pitch in the second direction. A ratio of the second pitch to the first pitch is 3:2.

Hybrid cell-based device, layout, and method

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Conductive rail structure for semiconductor devices

A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure also includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials, and the first oxide layer is in direct contact with the isolation layer, and a sidewall surface of the S/D structure is aligned with a sidewall surface of the first oxide layer.

Semiconductor device structure

Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Semiconductor devices including decoupling capacitors

A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

Field effect transistor with disabled channels and method

Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

Packaged semiconductor devices including backside power rails and methods of forming the same

Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure.

Backside interconnect structures for semiconductor devices and methods of forming the same

A semiconductor device includes a semiconductor layer, a gate structure, a source/drain epitaxial structure, a backside dielectric cap, and an inner spacer. The gate structure wraps around the semiconductor layer. The source/drain epitaxial structure is adjacent the gate structure and electrically connected to the semiconductor layer. The backside dielectric cap is disposed under and in direct contact with the gate structure. The inner spacer is in direct contact with the gate structure and the backside dielectric cap.

Semiconductor device and manufacturing method thereof

In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Semiconductor devices

A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature. The second gate electrode layer is disposed between the seventh and eighth source/drain epitaxial features.

Semiconductor device structure and methods of forming the same

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and semiconductor material layers stacked along a first direction over the substrate and spaced apart from each other. The semiconductor structure also includes inner spacers stacked along the first direction in spaces between the semiconductor material layers and a gate structure extending along a second direction and wrapping around the semiconductor material layers. In addition, the gate structure abuts a first side of the inner spacers. The semiconductor structure also includes a source/drain structure formed over the isolating feature and abutting the second side of the inner spacers.

Semiconductor structure with isolating feature

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Enhanced channel strain to reduce contact resistance in NMOS FET devices

A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

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Zhubei, Taiwan

Hou-Yu Chen