Intel Corporation

Hou-Jen Ko

Youfeng Wu

Sebastian Winkel

Jason M Agron

Oleg Margulis

Vineeth Mekkat

Girish Venkatasubramanian

Tyler N Sondag

Zhongying Zhang

Mark Dechene

John Faistl

Janghaeng Lee

A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.

Method and apparatus for supporting speculative memory optimizations

In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

Optimized call-return and binary translation

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Sunnyvale, CA, United States of America

Hou-Jen Ko