Intersil Americas Inc.

National Semiconductor Corporation

Foveon, Inc.

Hosam Haggag

Alexander Kalnitsky

Albert M Bergemont

Michael D Church

Edgardo A Laber

Min-hwa Chi

Carver A Mead

Yun Yue

Prabhjot Singh

A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Flash memory array of floating gate-based non-volatile memory cells

A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

Memory array of floating gate-based non-volatile memory cells

Bytes of cells in a Flash electrically-programmable read-only-memory (EPROM) are individually erasable by breaking each row of memory cells into byte-wide segments of memory cells, and utilizing a source access transistor with each segment of memory cells to control the source voltage on each segment of memory cells.

Flash eprom with byte-wide erasure

A capacitor coupled bipolar phototransistor having an integrated electronic shutter for reducing the overflow and blooming problems associated with the imaging of strong images. Overflow control and an anti-blooming mechanism are obtained by use of a second emitter (the 'shutter') which is used to remove excess image generated charge. This prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. The shutter is biased slightly lower than the first emitter of the phototransistor so that the base-shutter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. The overflow current of the generated holes is then drained to the shutter, rather than into the emitter where it would produce noise on the column sense line.

Capacitor-coupled bipolar active pixel sensor with integrated electronic

A capacitor coupled contactless imager structure and method of manufacturing the structure results in a phototransistor that includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the imager phototransistor. Silicon dioxide separates the polysilicon emitter contact and exposed surfaces of the base region from a layer of poly2 about 500-600 .ANG. thick that is formed to cover the entire base region.

Method of manufacturing a thin poly, capacitor coupled contactless

The size of an active pixel sensor cell is reduced by utilizing a single MOS transistor formed in a well to perform the functions conventionally performed by a photogate/photodiode, a sense transistor, and an access transistor. Light energy striking the well varies the potential of the well which, in turn, varies the threshold voltage of the transistor. As a result, the current sourced by the transistor is proportional to the received light energy.

Single MOS transistor active pixel sensor cell with automatic

A capacitor coupled contactless imager structure and a method of manufacturing the structure results in a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter content and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.

Method of manufacturing a capacitor coupled contactless imager with high

A technique for decreasing the effective gain of a bipolar phototransistor at high light levels makes the image usable over a greatly extended range of illumination conditions. The effective current gain at high light levels is reduced by fabricating a 'non-ideal' emitter, such as by inserting a thin 20 521 tunnel oxide between the emitter and base junction. The tunnel oxide between the emitter and base serves as a variable resistor as well as a good junction for carrier injection from the emitter. The total base voltage is the sum of the oxide voltage and the intrinsic base voltage. At high image intensity, the bipolar phototransistor will gradually enter into the saturation mode, i.e., the base to collector junction is forward biased. The beta is thus reduced. The bias of the collector should be about 0.3-0.8 V higher than the emitter at the 20.ANG. tunnel oxide thickness for optimum operation.

Base capacitor coupled photosensor with emitter tunnel oxide for very

A capacitor coupled contactless imager structure and a method of manufacturing the structure results is a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface to the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter contact and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.

Growing community of inventors

Mountain View, CA, United States of America

Hosam Haggag