Broadcom Corporation

Agere Systems Inc.

Avago Technologies International Sales Pte. Limited

Hosahalli Rajarao Srinivas

Amy Gayle Hundhausen

Erik Berg

Gopal Triplicane Venkatesan

Prashant Katre

Alexander Goldovsky

Amit Rajendra Agarwal

Gregory J Goodemote

James Ching-Shau Yik

Bismaya Parida

A device implementing the subject wireless communication system may include one or more memories, and one or more processors coupled to the one or more memories. In some aspects, the one or more processors are configured to cause receiving a first frame comprising an indication that the station has data buffered at an access point, determining, in response to the first frame, whether a measured buffer depth exceeds a predetermined threshold, receiving a second frame comprising a predetermined amount of buffered data based on the measured buffer depth, transitioning, after the predetermined amount of buffered data is received, into a sleep mode for a first predetermined duration when the measured buffer depth exceeds the predetermined threshold, and transitioning into the sleep mode for a second predetermined duration less than the first predetermined duration when the measured buffer depth does not exceed the predetermined threshold.

Power consumption optimization of wireless communication systems for content delivery

An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

BTSC pilot signal lock

An integrated digital BTSC encoder is implemented on a single CMOS integrated circuit chip with an all digital RF modulator. A set top box is provided that allows for a fully integrated solution which may be used with legacy television systems and also with other audio/visual equipment connected to the set top box.

Integrated circuit BTSC encoder

An BTSC encoder with an improved digital filter structure substantially implemented on a single CMOS integrated circuit is described. By cascading first and second order allpass filter structures to form a higher order digital filter, such as a Cauer low pass filter, limit cycle oscillations are reduced or eliminated, word-length growth from one stage to the next is contained, and a more efficient overall filter structure and performance is obtained.

Mechanism for using the allpass decomposition architecture for the cauer low pass filter used in a BTSC

An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit is described. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

An integrated digital BTSC encoder substantially implemented on a single CMOS integrated circuit is described. By saturating and adding offsets to the value of the feedback control signal in regions of operation where the calculation for the control signal is dominated by noise, an integrated circuit selectively adjusts the control signal for the spectral or wideband feedback loop, as required, so that the performance of a very low noise digital BTSC encoder complies with the requirements of the BTSC standard.

Mechanism for using clamping and offset techniques to adjust the spectral and wideband gains in the feedback loops of a BTSC encoder

An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. The computation stages for each of the bit positions include a sum computation stage implemented in logic circuitry. For a subset of the bit positions, the corresponding sum computation logic circuitry computes a sum based at least in part on group-generate, group-transmit and intermediate carry signals. Advantageously, the sum computation logic circuitry is configured to exploit differences in delay associated with generation of the group-generate, group-transmit and intermediate carry signals, so as to reduce the total computational delay of the adder. Additional delay reduction may be achieved by configuring the sum computation stages of the adder in accordance with a left-to-right routing of the group-generate and group-transmit signals, such that a most-significant half of a given set of sum bits are generated in the same prefix trees as a least-significant half of the sum bits.

Growing community of inventors

Irvine, CA, United States of America

Hosahalli Rajarao Srinivas