Asea Brown Boveri Ag

Asea Brown Boveri Inc.

Bbc Brown Boveri Ag

Abb Research Ltd.

Abb Management Ag

Horst Gruning

Jens Gobrecht

Jan Voboril

Jochen Rees

Herbert Stemmler

Osvin Gaupp

Friedhelm Bauer

Philippe Maibach

Peter Dahler

Bruno Broich

Helmut Keser

Conrad Beriger

Bjorn Odegard

Sven Klaka

Thomas Keller

Ferdinand Steinruck

C Christiaan Abbas

Herve De Lambilly

Enrico Piccioni

Alexander Klett

A semiconductor component including a housing for a semiconductor substrate, an anode, a cathode, an annular gate electrode flange, which laterally protrudes from the housing and concentrically surrounds the housing, and an annular auxiliary cathode flange, which protrudes from the housing and makes contact with the cathode.

Gate controlled thyristor driven with low-inductance

The invention specifies a disconnector for decoupling a load from a supplying AC voltage network. The disconnector comprises at least one disconnector stage having a series circuit comprising at least two reverse-conducting gate turn-off thyristors which are connected cathode to cathode. The gate turn-off thyristors are preferably hard driven. This allows the use of a single circuit capacitor in parallel with the series-connected gate turn-off thyristors. This embodiment has the advantage that, during disconnection, the current commutates early from the gate turn-off thyristors, which means that the disconnection capacity can be increased.

High-speed disconnector using semiconductor technology

In a gate unit (47) for a hard-driven GTO (10), at least some of the electronic components (37, . . , 42) needed for driving are arranged on a printed circuit board (34). The printed circuit board (34) encloses the GTO (10), in order to achieve low-inductance contact, in a plane lying between the anode side and the cathode side of the GTO (10) parallel to the semiconductor substrate (17) of the GTO (10) and is directly connected to the cathode contact (14) and the gate connection (22) of the GTO (10). A compact structure with, at the same time, improved mechanical stability is achieved in such a gate unit in that the components (37, . . , 42) are arranged on the printed circuit board (34) around the GTO (10), in the immediate vicinity of the GTO (10).

Gate unit for a hard-driven GTO

A power converter circuit arrangement which comprises a first power converter and at least one further power converter is specified. The power converters are connected to the DC voltage intermediate circuit and feed a load circuit, in particular a single-phase railway grid. The or each further power converter has an output transformer on the load side. The secondary windings of the output transformers are connected in series with the primary winding of a load transformer, which feeds the load circuit, and the load-side terminals of a first power converter. This permits the turns ratios of the output transformers to be selected to be greater than or equal to one and said turns ratios between said output transformers to be selected to be gradated in a binary or ternary manner, for example. As a result, power converter stages having a gradated output voltage are available, and a finely stepped approximation to a sinusoidal output voltage can be achieved without the necessity of providing an uneconomically large number of stages.

Power breaker

A converter is specified which is distinguished in that a bus system is provided between the paths of a phase module of the converter and allows potential chambers to be formed around the semiconductor switches and/or the circuitry elements. The potential chambers surround the semiconductor switches and the circuitry elements. They comprise two longitudinal metal sheets which are arranged to be insulated from one another, in particular overlapping. In addition, transverse metal sheets may be provided, which are connected to the connections of the semiconductor switches and/or circuitry elements. The potential chambers result in each potential chamber having a potential difference which is only a fraction of the intermediate circuit voltage. The bus system carries out the insulation of the high potential difference corresponding to the intermediate circuit voltage.

Low-inductance converter

A power electronic circuit arrangement which comprises a first power converter is specified. A second power converter is connected between the load terminals of the first power converter and a load. The negative or positive values of the DC voltage intermediate circuits of the first and second power converters can be added by means of corresponding driving of the power converters. This achieves finer voltage gradation and, consequently, an improved approximation of the resulting output voltage to the sinusoidal waveform.

Power electronic circuit arrangement having plural power converters

A converter circuit arrangement is disclosed. As a result of the fact that GTOs are hard driven, reverse-parallel connected diodes have a reverse current response dV/dt of 2 kV/.mu.s to 10 kV/.mu.s and a low-inductance freewheeling circuit is provided between the DC voltage source and the GTOs, the GTOs and the reverse-parallel connected diodes can be operated without a protective circuit.

Converter circuit arrangement

A converter circuit arrangement in which the gate turn-off thyristors are driven hard, i.e., the GTO is driven with a gate current configured in such a way that the turn-off gain IS/IGpeak is distinctly less than 3 so as to result in an anode voltage rise of at least 1 kV/.mu.s. The snubber circuit of such driven thyristors may be designed to include only a small number of elements. The voltage rise limiter includes at least one capacitor connected in parallel with one of the reverse-connected parallel diodes. The current rise limiter includes a parallel circuit having an inductor and a current limiting diode.

Converter circuit arrangement with minimal snubber

A converter circuit arrangement is specified in which actively controllable current and voltage rise limiting means are provided in parallel with a semiconductor switch. These means also take over the function of a reverse-connected parallel diode and essentially comprise a bipolar transistor which is driven by a control circuit.

Converter circuit arrangement with actively controllable current and

A converter circuit arrangement is specified which is constructed to have a particularly low inductance. This is achieved by the circuit area of the commutation circuit being kept as small as possible. A circuit area which is as small as possible is achieved by the branch modules and switch modules of a phase module being arranged either in a U-shape or in a meandering shape. The branch modules can be arranged either parallel to or at right angles to a main direction, between the positive and negative connections and the load connection. In addition, it is advantageous if the power semiconductor switches and the reverse-connected parallel diodes and freewheeling diodes are arranged in separate stacks which are held together by means of a clamping-in device.

Converter arrangement having a low-inductance commutation circuit

Gate circuit for hard driven GTO

In a turn-off high-power semiconductor component, in particular in the form of a GTO, comprising a disk-shaped semiconductor substrate (2) which is disposed concentrically in an annular insulating housing (10) between a disk-shaped cathode contact (4), to which pressure can be applied, and a disk-shaped anode contact (5), to which pressure can also be applied, and which is contacted on the cathode-contact side by a gate contact (7, 21), the cathode contact (4) being connected to one end of the insulating housing (10) via a first lid (11a) and the anode contact (5) to the other end of the insulating housing (10) via a second lid (11b), an outwardly hermetically sealed component (1) being formed, and the gate contact (7) being capable of being fed with a gate current via a gate lead (8) brought to the outside, a connection to the gate unit is achieved with low mutual inductance with a minimum of alterations compared with conventional components as a result of the gate lead (8) being of rotationally symmetrical design and being disposed concentrically with respect to the cathode contact (4) and of the gate lead (8) being electrically isolated from the cathode contact (4) by a single insulator.

Turn-off high-power semiconductor component with low inductive housing

A switching arrangement for an RF-GTO is specified. It comprises a latching-type semiconductor component (GTO) of familiar construction. The circuit for turning off the semiconductor component (GTO) is designed in such a manner that the turn-off gain I.sub.A /I.sub.G, peak is distinctly less than 3 and, in particular, less than or equal to 1. During the turning-off, the drive is hard, that is to say has a high rate of increase dI.sub.G /dt and high current. A capacitance (C.sub.p) is connected directly in parallel with the semiconductor component (GTO).

Switching arrangement for an RF GTO

In an inverter with overload current projection, a half-bridge is divided in module form into two quarter-bridge branches. Disposed in the latter are a gate turn-off semiconductor component (7, 8), a freewheeling diode (9, 10) situated opposite with respect to a center point and a blocking capacitor (11, 12) in parallel with freewheeling diode (9, 10) and turn-off semiconductor component (7, 8). A measuring resistor (R1, R2) and a current-limiting component (L1, L2) are provided between a load terminal (3) of the bridge circuit and the center points of the quarter-bridge branches. The load current can be determined in a transient-free manner with the measuring resistors.

Inverter with overload current protection

A power semiconductor circuit comprises a gate-turn-off semiconductor component (FCTh1, FCTh2) having an anode, a cathode and a gate, a diode (D1, D2) and a drive circuit which is connected to the gate by a large-area, low-inductance stripline (11) and which generates a current pulse for turning off the semiconductor component. The diode (D1, D2) is arranged in series with the semiconductor component (FCTh1, FCTh2), specifically in such a way that the diode (D1, D2) and semiconductor component (FCTh1, FCTh2) form a quarter-bridge arm. Provided in parallel with the series circuit of the semiconductor component (FCTh1, FCTh2) and diode (D1, D2) is a low-inductance blocking capacitor (C1, C2) for absorbing the reverse recovery voltage peaks of the diode (D1, D2). The diode (D1, D2) and blocking capacitor (C1, C2) are arranged with low inductance and spatially immediately adjacent to the semiconductor component.

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Wettingen, Switzerland

Horst Gruning