Infineon Technologies Ag

Intel Corporation

Intel Deutschland Gmbh

Horst Baumeister

Roland Gessner

Eberhard Veuhoff

Gundolf Wenger

Hans-Joachim Barth

Georg Seidemann

Bernd Waidhas

Peter Baumgartner

Philipp Riess

David O'Sullivan

Bernd Borchert

Alois Nitsch

Rainer Tilgner

Jesenka Veledar Krueger

IC chip package routing structures including a metal-insulator-metal (MIM) capacitor integrated with redistribution layers. An active side of an IC chip may be electrically coupled to the redistribution layers through first-level interconnects. The redistribution layers terminate at interfaces suitable for coupling a package to a host component through second-level interconnects. The MIM capacitor structure may comprise materials suitable for high temperature processing, for example of 350° C., or more. The MIM capacitor structure may therefore be fabricated over a host substrate using higher temperature processing. The redistribution layers and MIM capacitor may then be embedded within package dielectric material(s) using lower temperature processing. An IC chip may be attached to the package routing structure, and the package then separated from the host substrate for further assembly to a host component.

Integrated circuit package redistribution layers with metal-insulator-metal (MIM) capacitors

A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.

Detection of environmental conditions in a semiconductor chip

A method for detecting a crack in a semiconductor wafer, which includes an electrical device and a connecting pad electrically coupled with the electrical device, is described. The crack is detected by an acoustic detector being acoustically coupled to the semiconductor wafer during contacting the contacting pad with a probe.

Method and apparatus for detecting a crack in a semiconductor wafer, and a wafer chuck

The invention relates to a method for fabricating a structure in a semiconductor material. At least one etching step is carried out in-situ in an epitaxy installation and tertiary butyl chloride is used as the etchant. The at least one etching step produces at least one grating structure of a DFB laser. This provides an efficient method for fabricating DFB lasers.

Method for the in-situ fabrication of DFB lasers

A method produces structures for semiconductor components, particularly BH laser diodes, in which a mask material is applied to a sample in a masking step. The etch rate in an etching step depends upon the composition and/or nature of the mask material. The etch rate is selected in such a way so that the mask is at least partly dissolved during the etching step. It is therefore possible to easily remove the mask from the semiconductor material and apply additional layers in situ during the fabrication of semiconductor components.

Masking method for producing semiconductor components, particularly a BH laser diode

Method of producing a structure for III-V semiconductor components in which a mask is applied to a sample in a masking step, characterized in that at least one mask material is a monocrystalline III-V semiconductor material. This makes possible an easy in-situ removal of the mask from the semiconductor material, which in turn makes possible the growing of additional layers.

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Munich, Germany

Horst Baumeister