Super Talent Electronics, Inc.

Horng-Yee Chou

Charles Chung Lee

Szu-Kuang Chou

Ren-Kang Chiou

Sun-Teck See

Ben Wei Chen

I-Kang Yu

Kuang-Yu Wang

Abraham C Ma

Ming-Shiang Shen

David Q Chow

Frank Yu

Edward W Lee

Tzu-Yih Chu

I-pieng Peter Kao

Edward Kihyen Lee

Systems and methods for communicating using various protocols through the Secured Digital (SD) physical interface are disclosed. The invention covers, among others, single-mode and multi-mode hosts, single-mode and multi-mode devices, as well as techniques for initializing these hosts and devices in order to facilitate the aforementioned communication.

Extended Secure-Digital (SD) devices and hosts

A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

PCI express-compatible controller and interface that provides PCI express functionality and flash memory operations to host device

A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultimediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

Differential data transfer for flash memory card

Extended secure-digital (SD) devices and hosts

An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.

Chained DMA for low-power extended USB flash device without polling

A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultiMediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

An extended universal-serial bus (EUSB) bridge to a host computer can have peripheral component interconnect express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.

High-level bridge from PCIE to extended USB

PCI express-compatible controller and interface for flash memory

Extended Universal-Serial-Bus (USB) plugs and sockets are disclosed. The extended USB plug includes an extended pin substrate having an extended substrate length longer than a length of a pin substrate of an industry-standard USB connector plug. There is further included a plurality of USB connector contacts configured to carry USB signals and a plurality of non-USB connector contacts configured to carry non-USB signals. The extended Universal-Serial-Bus (USB) plug, which includes an extended pin substrate having an extended substrate length longer than a length of a pin substrate of an industry-standard USB connector plug. There is included a plurality of USB connector contacts configured to carry USB signals and a plurality of non-USB connector contacts configured to carry non-USB signals.

Extended UBS protocol connector and socket

The present invention relates to a method and system for providing a flash memory assembly. The flash memory assembly includes a connector and a printed circuit board (PCB) coupled to the connector. The center of the PCB is positioned substantially at the center of the connector. An electronic component is coupled to one side of the PCB. In another aspect of the present invention, a second electronic component is coupled to a second side of the PCB. In another aspect of the present invention, the electronic components and the PCB are protected by covers joined using interference fitting or ultrasonic joining. In another aspect of the present invention, a cap protects the connector. The cap can be removably coupled to the connector.

System and method for providing a flash memory assembly

A memory flash card reader includes a processor for receiving at least one request from a host system, an index comprising information regarding sectors of the memory flash card wherein the processor may utilize the index to determine sectors of the memory flash card that are available for programming, reprogramming, or reading, and at least one card controller coupled to the processor.

Memory flash card reader employing an indexing scheme

A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

Flash memory system with a high-speed flash controller

A peripheral device having a device processor, a multi-personality bus switch, and an extended Universal-Serial Bus (USB) plug is disclosed. The peripheral device is capable of communicating with a host computer using one or more protocols. The extended Universal-Serial Bus (USB) plug includes an extended pin substrate, the extended pin substrate and at least some of a plurality of contacts thereon being dimensioned to be mechanically compatible with an industry-standard USB socket. The extended USB plug further lacks an industry-standard cover associated with an industry-standard USB plug, thereby causing the extended USB plug to be thinner than the industry-standard USB plug.

Peripheral device having an extended USB plug for communicating with a host computer

An extended Universal-Serial Bus (USB) plug and extended Universal-Serial Bus (USB) socket are disclosed. The extended Universal-Serial Bus (USB) plug includes an extended pin substrate, the extended pin substrate and at least some of a plurality of contacts thereon being dimensioned to be mechanically compatible with an industry-standard USB socket. The extended USB plug further lacks an industry-standard cover associated with an industry-standard USB plug, thereby causing the extended USB plug to be thinner than the industry-standard USB plug. The extended Universal-Serial Bus (USB) socket, which includes an extended cavity having an extended cavity length longer than a length of a cavity of an industry-standard USB connector socket. The extended cavity and at least some of a plurality of pins therein are dimensioned to be mechanically compatible with an industry-standard USB connector plug.

Connectors having a USB-like form factor for supporting USB and non-USB protocols

A serial flash-memory chip has a serial-bus interface to an external controller. A flash-memory block in the serial flash-memory chip can be read by the external controller sending a read-request packet over the serial bus to the serial flash-memory chip, which reads the flash memory and sends the data back in a data-payload field in a completion packet. Data in a write-request packet is written to the flash memory, and a message packet sent back over the serial bus. The serial bus can be a Peripheral Component Interconnect (PCI) Express bus with bi-directional pairs of differential lines. Packets have modified-PCI-Express headers that define the packet type and data-payload length. Vendor-defined packets can send flash commands such as reset, erase, or responses after operations such as program or erase. A serial engine and microcontroller or state machine are on the serial flash-memory chip.

Growing community of inventors

Palo Alto, CA, United States of America

Horng-Yee Chou