Taiwan Semiconductor Manufacturing Comp. Ltd.

Horng-Wen Chen

Chi-How Wu

Ming-Shuo Yen

Chiang-Jen Peng

Chen-Yu Chang

Pei Hung Chen

Jeng-Fieng Lu

A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for MOS devices. A hard mask layer is provided overlying the polysilicon layer. A resist layer is provided overlying the hard mask layer. The resist layer is patterned to form a resist mask the exposes a part of the hard mask layer. The polysilicon layer is patterned in a plasma dry etching chamber. First, the resist layer is optionally trimmed by etching. Second, the hard mask layer is etched where exposed by the resist mask to form a hard mask that exposes a part of the polysilicon layer. Third, the resist mask is stripped away. Fourth, polymer residue from the resist mask is cleaned away using a chemistry containing CFgas. Fifth, the polysilicon layer is etched where exposed by the hard mask. After the polysilicon layer is so patterned in the dry plasma etch chamber, the hard mask layer is stripped away to complete the patterning of the polysilicon layer in the manufacture of the integrated circuit device.

In-situ strip process for polysilicon etching in deep sub-micron technology

A method for determining the number of contaminating particles in a process chamber is described. While the method is particularly suited for detecting particles in a metal etch chamber, the present invention novel method can be utilized in any other semiconductor process chambers as long as there is a particle contamination problem. The method is carried out by conducting at least two particle dislodging cycles each including a step of flowing at least one process gas used in the process into the chamber at a flow rate of at least 30 sccm, and then evacuating the at least one process gas from the chamber to a pressure of not higher than 1 mTorr. Typical process gas that can be utilized in a metal etch chamber includes Cl , BCl and Ar. The process gas should be flown into the etch chamber until a chamber pressure of at least 6 mTorr is reached, and preferably until at least a chamber pressure of 8 mTorr is reached. After the particle dislodging cycles are conducted, the number of particles that have fallen onto a top surface of the substrate can be counted by a particle counter.

Method for monitoring contaminating particles in a chamber

A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for MOS devices. A hard mask layer is provided overlying the polysilicon layer. A resist layer is provided overlying the hard mask layer. The resist layer is patterned to form a resist mask the exposes a part of the hard mask layer. The polysilicon layer is patterned in a plasma dry etching chamber. First, the resist layer is optionally trimmed by etching. Second, the hard mask layer is etched where exposed by the resist mask to form a hard mask that exposes a part of the polysilicon layer. Third, the resist mask is stripped away. Fourth, polymer residue from the resist mask is cleaned away using a chemistry containing CF,gas. Fifth, the polysilicon layer is etched where exposed by the hard mask. After the polysilicon layer is so patterned in the dry plasma etch chamber, the hard mask layer is stripped away to complete the patterning of the polysilicon layer in the manufacture of the integrated circuit device.

A process for determining particles in a dry etching system, prior to performing the dry etching definition of a desired pattern, has been developed. The process features a two cycle, dry etching procedure, with the first cycle performed using a first set of dry etching conditions, not robust enough to result in etching of exposed material, but robust enough do allow the activation, and operation, of a backside helium alarm procedure, used to monitor particle count in the dry etching chamber, to be realized. If particle counts are acceptable a second cycle of the dry etching procedure, using a second set of dry etching conditions, is employed to define the desired pattern. If the particle counts observed via use of the backside helium alarm procedure during the non-etching, first cycle, are high, the dry etching procedure is interrupted. After cleanup of the dry etching chamber, the same samples, with a re-worked photoresist, are again subjected to the two cycle, dry etching procedure.

Method for initiating a helium alarm particle detector in a dry etching system prior to initiation of the etching process

A method that teaches the formation of deep trenches within the surface of a semiconductor wafer, these deep trenches are used to separate the wafer into individual chips by applying stress to the wafer. The formation of the deep trenches uses exposing a thick layer of photoresist followed by etching. The etching is a two step etch, a stabilization etch and a main etch. The stress used to separate the wafer into individual chips can be invoked by applying physical force to the wafer.

Method to increase wafer utility by implementing deep trench in scribe line

A process is described for etching contact holes though a dielectric layer down to a silicon surface. Initial etching, until the silicon is exposed, is performed in a suitable plasma environment under high RF power. This results in damage to the newly exposed silicon surface. Said damage is repaired by exposing the silicon and the photoresist to an atmosphere that includes carbon tetrafluoride and atomic oxygen. The latter oxidizes the damaged layer, allowing it to be removed by the former. Much of the photoresist is also removed by the atomic oxygen, any that still remains being then removed using a wet etch. At the user's option, the silicon may be allowed to overetch during the high RF power application and/or a low power RF step may be introduced to partially remove silicon surface damage prior to the atomic oxygen treatment.

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Taichung, Taiwan

Horng-Wen Chen