United Microelectronics Corp.

Horng-Non Chern

Kun-Chi Lin

Tsu-An Lin

Alex Hou

Chien-Hua Tsai

A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate. Removing the first photoresist layer and the fourth dielectric layer of the interior circuit, a fifth dielectric layer is formed on the third dielectric layer of the interior circuit. The fourth dielectric layer and the top surface of the second dielectric layer of the peripheral circuit are removed. The fifth dielectric layer is formed on the first dielectric layer and the third peripheral of the peripheral circuit, and then the second photoresist layer on the fifth dielectric layer, wherein the third photoresist layer is patterned as a bit-line contact via of the interior circuit and the bit-line contact vias of the peripheral circuit. Finally, anisotropically etching the third photoresist layer and the fifth dielectric layer, a bit-line to the substrate contact via and a bit-line to the gate contact via are formed inside the fifth dielectric layer.

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Chia-Li Jen, Taiwan

Horng-Non Chern