Realtek Semiconductor Inc.

Mstar Semiconductor, Inc.

Horng-Der Chang

Chao-Cheng Lee

Sterling Smith

Kuo-Feng Hsu

Henry Tin-Hang Yung

Chia-Ming Yang

Zhi-Ren Chang

Chao-Ping Huang

Chi-Han Lan

Shin-Ing Hsieh

The present invention discloses an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission comprising: a first transistor, a second transistor, a resistor, a negative feedback control circuit, a multiplexer and a reference voltage generator. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.

Impedance matching circuit

An audio processing circuit includes a clock synthesizer, a clock divider, a digital interpolator module, a sampling rate converter and a digital-to-analog converter. The clock synthesizer generates a base clock signal according to a sampling clock signal and a first reference clock signal. The clock divider generates a multiple frequency clock signal according to the base clock signal. The digital interpolator module interpolates a digital audio data according to the multiple frequency clock signal. The sampling rate converter processes the interpolated digital audio data into a re-sampled digital audio data according to the multiple frequency clock signal and a second reference clock signal. The digital-to-analog converter is coupled to the sampling rate converter for converting the re-sampled digital audio data into an analog audio signal according to the second reference clock signal.

Audio processing circuit and method

A clock generator capable of providing reduced low-frequency jitter clock signals without utilization of a crystal oscillator is introduced. The present invention clock generator utilizes a diode in related biasing circuit such that the generated control current to a current control oscillator is stable and clear due to the low flicker noise and low thermal noise of the voltage across the diode. The cost of PLL systems utilizing the present invention clock generator instead of a crystal oscillator is decreased. The adopted biasing circuit is introduced as well.

Clock generator and related biasing circuit

A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.

Video signal processing system including analog to digital converter and related method for calibrating analog to digital converter

A hybrid phase-locked loop, comprising: a phase-frequency detector, for detecting the phase difference between a reference signal and an oscillation feedback signal and generating a digital phase-difference signal according to a mean-frequency signal; a digit pump, for receiving the phase-difference signal and generating a proportional gain signal and an accumulative gain signal according to a proportional gain value and an accumulative gain value; a digital filter, for receiving the proportional gain signal and the accumulative gain signal so as to generate a digital control signal; a digit-controlled oscillator (DCO), for receiving the control signal and the mean-frequency signal so as to generate a phase-swap signal; a phase selector, for receiving a plurality of multi-phase signals and the phase-swap signal so as to select one among neighboring phases to be the mean-frequency signal according to the phase-swap signal; an analog phase-locked loop, for receiving the mean-frequency signal and filtering out the cycle-to-cycle jitter thereof so as to generate an output signal; and a frequency divider, for receiving the output signal and dividing the frequency thereof so as to generate the oscillation feedback signal.

Hybrid phase-locked loop

A circuit includes a first voltage-controlled oscillator (VCO) that generates a feedback clock. The circuit further includes a phase frequency detector, a charge pump and a loop filter that together receive a reference clock and the feedback clock, and in response thereto, generates a first voltage signal. The circuit further includes a timing generator that generates a control signal having varying periods, and a voltage modulator that receives the first voltage signal and the control signal, and in response thereto, generates a second voltage signal and a third voltage signal. The second voltage signal is provided to the first VCO. The circuit also includes a second VCO that receives the third voltage signal and which outputs a spread spectrum clock.

Phase-locked loop circuit capable of adjusting the frequency range of spread spectrum clock

The present invention discloses a glitch-free frequency dividing circuit, comprising: a frequency dividing module, dividing the frequency of a reference pulse according to the divisor, outputting a frequency divided output pulse and receiving a control signal such that the state of the frequency divided output pulse is maintained the same when the control signal is enabled; and a latch module, detecting the state of the frequency divided output pulse after a divisor switching signal is received, enabling the control signal when the frequency divided output pulse is as pre-determined, switching the divisor when the frequency divided output pulse is as pre-determined and disabling the control signal after the divisor is switched; whereby the generation of the glitch is prevented during the switching of the divisor.

Glitch-free frequency dividing circuit

The present invention provides a phase-locked loop having a multi-phase voltage controlled oscillator. The phase-locked loop comprises a divided-by-N counter, a divided-by-M counter, a phase frequency detector, a charge pump, a loop filter, a multi-phase voltage controlled oscillator, a switching unit, and a clock counter. It utilizes a multi-phase voltage controlled oscillator instead of a conventional voltage controlled oscillator and a switching unit is used to select the output signal from the multi-phase voltage controlled oscillator. The switching time of the switching unit is controlled by the clock counter to achieve the effect of frequency expansion.

Phase-locked loop having a multi-phase voltage controlled oscillator

A phase-locked loop which achieves the effect of frequency expansion is disclosed. An adjustable delay element is incorporated in a conventional phase-locked loop in order that one of the output clock signals of a divided-by-N counter and a divided-by-M counter leads (lags behind) the other. This in turn causes a phase frequency detector to alternately generate `up` and `dn` signals, thereby frequency expansion is achieved.

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Hualien, Taiwan

Horng-Der Chang