National Science Council

Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Industrial Technology Research Institute

National Science Council of Republic of China

Other

S.m. Sze

Horng-Chih Lin

Tiao-Yuan Huang

Hong-Nien Lin

Chun-Yen Chang

Ming-Hsien Lee

Chi-Chun Chen

Chen-Pang Kung

Huai-Yuan Tseng

Chun-Jung Su

Liang-Po Chen

Hsiao-Yi Lin

Tien Sheng Chao

Rong-Jhe Lyu

Jien-Sheng Chao

Yu-An Huang

Hsing-Hui Hsu

Guan-Jang Li

Hsin-Hwei Hsu

Ming-Shih Tsai

A radio frequency integrated circuit includes a silicon CMOS substrate with at least one CMOS device buried therein, and at least one thin film transistor formed on the silicon CMOS substrate and functioning as a radio frequency device. The thin film transistor includes a T-shaped gate electrode. A method for the fabricating a radio frequency integrated circuit is also disclosed.

Radio frequency integrated circuit having relatively small circuit area and method of fabricating the same

A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.

Body-tied, strained-channel multi-gate device and methods

Body-tied, strained-channel multi-gate device and methods of manufacturing same

A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.

A method for fabricating a thin-film transistor is disclosed. Firstly, a patterned dielectric mask structure with a bottom thereof having a gate dielectric layer is formed on a gate-stacked structure so that the gate dielectric layer covers a gate of the gate-stacked structure. Top surface of the patterned dielectric mask structure has at least two openings. A semiconductor layer is formed on the gate-stacked structure via the openings by a sputtering method. The semiconductor layer comprises a channel above the gate, a source and a drain below the openings. The channel has a thickness which sequentially decreases from edge to center.

Method for fabricating thin-film transistor

The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.

Suspended nanochannel transistor structure and method for fabricating the same

A method of fabricating a semiconductor device includes first providing an insulation substrate. A patterned conductive layer is formed over the insulation substrate, and the patterned conductive layer includes a channel region and a number of protruding regions. A gate structure layer is formed over the insulation substrate. The gate structure layer covers a part of the patterned conductive layer, and each of the protruding regions has an exposed region. A doping process is performed to dope at least the exposed region of the patterned conductive layer to form a number of S/D regions.

Method of fabricating semiconductor device

A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A nonvolatile memory device with nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has the capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished.

Nonvolatile memory device with nanowire channel and method for fabricating the same

A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and each of the S/D electrode pairs has a different extension direction with respect to the channel layer. A gate dielectric layer is disposed on the channel layer. A gate layer is disposed on the gate dielectric layer. Preferably, for example, the extension direction of at least one of the S/D electrode pairs is a first direction, and the extension direction of at least another one of the S/D electrode pairs is a second direction.

Structure of semiconductor device

A novel structure of nonvolatile memory is formed on p type silicon and includes a stacked gate, a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One side of the stacked gate has a source region and the other has a drain region, wherein the surface of the source region includes a thin metal silicide connected with a channel region to form a Schottky barrier. A tilted angle implant with As or P doping is performed on the p type silicon substrate to form a drain region and extend a portion of the drain region to a channel region under the stacked gate. For implanting, an n doped source region is also formed, creating an offset between the source region and the channel region as a result of the tilted angle implant. For programming, the source region is grounded, positive voltage is applied to the drain region and the gate, such that the hot carriers inject into the floating gate through the channel adjacent to the source region.

Nonvolatile memory having a split gate

The present invention discloses a thin film transistor with sub-gates and Schottky source/drain and a method of manufacturing the same. Doping of source/drain, and the following annealing steps used conventionally are omitted and the complexity of process and process costs are reduced. The temperature of the process is also decreased. A thin film transistor with sub-gates and Schottky source/drain of the invention is able to operate in both the n type and p type channel modes on the same transistor element depending on the biased voltage of the sub-gate. Moreover, an electric junction is formed by induction, using bias voltage applied on the sub-gate, which takes the place of the conventional source/drain extensions. Consequently, the off-state leakage current is reduced.

Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the same

A method of reducing the boron-penetrating of effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, boron ions (B ) are doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to form a polysilicon gate. The gate photoresist is used as a mask to dope boron difluoride ions (BF ) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain region on the silicon substrate.

Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect

A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is formed on an element area of a silicon substrate. Then, a polysilicon layer is deposited on the gate oxide layer. Next, a gate doping process and a fluorine ion implantation are performed on the polysilicon layer. Then, a high-temperature tempering procedure is performed to make the fluorine enter the gate oxide layer.

Method of forming a gate oxide layer with an improved ability to resist the process damage

A method is provided for selective oxidation on source/drain regions of transistors on an integrated circuit. The method includes the steps of a) incorporating a neutral species into first kind of the source/drain regions, and b) forming oxidation regions over the first kind of source/drain regions and second kind of the source/drain regions, wherein the oxidation regions over the second kind are thicker than the oxidation regions over the first kind.

Growing community of inventors

Hsinchu, Taiwan

Horng-Chih Lin