Micron Technology Incorporated

Avago Technologies General IP (Singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Seagate Technology Incorporated

Lsi Corporation

Western Digital Technologies, Inc.

Quantum Corporation

Horia Cristian Simionescu

Timothy E Hoglund

Gowrisankar Radhakrishnan

Sridhar Rao Veerla

Panthini Pandit

Mark Ish

Luca Bert

Sumanesh Samanta

Chung Kuang Chin

Paul Roger Stonelake

Anant Baderdinni

Robert L Sheffield

Sujan Biswas

Jung Sheng Hoei

Peng-Cheng Chen

Rohitkumar Makhija

Narasimhulu Dharanikumar Kotte

Robert Michael Walker

Jiangli Zhu

Fangfang Zhu

Lyle E Adams

Samir Mittal

Chih-Kuo Kao

Anirban Ray

Gurpreet Anand

Kapil Sundrani

James A Rizzo

Yueh-Hung Chen

Adam Weiner

Kunal Sablok

Xiaodong Wang

Yongcai Xu

Venkata Yaswanth Raparti

Earl T Cohen

Timothy Lawrence Canepa

Michael Stephen Rothberg

Shashank Nemawarkar

Gregory B Thelin

Prateek Sharma

Balakrishnan Sundararaman

Cagdas Dirik

Naveen Krishnamurthy

Kishore Kaniyar Sampathkumar

Saugata Das Purkayastha

Anirban Kundu

Clifford M Gold

James A Henson

Shailendra Aulakh

Robert Quinn

James K Yu

Raja V S Halaharivi

Siddhartha Kumar Panda

Eric L Severtson

Mohana Rao Goli

Rajeev Srinivasa Murthy

Di Hsien Ngu

Allen Kelton

Larry Stephen King

Robert W Walker

Siddartha Kumar Panda

Veera Kumar Reddy Oleti

Debal Kr Mridha

Anand Narayanamurthy

John Edward Lauber

Luan Kha Bui

Ramkumar Venkatachalam

Robert L Sheffield Jr

Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.

Memory management

In some implementations, a memory device may obtain, from a host device, a first one or more commands associated with a first identifier. The memory device may maintain a first counter associated with tracking active commands from the host device. The memory device may detect an event, associated with a command, at a first time. The memory device may switch, based on detecting the event, an active identifier for commands obtained after the first time to a second identifier. The memory device may initiate a second counter associated with tracking active commands that were obtained prior to the first time. The memory device may perform an action associated with a command that is associated with the first identifier. The memory device may update, based on performing the action, the first counter and the second counter based on the at least one command being associated with the first identifier.

Memory device active command tracking

Disclosed is a system comprising a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying a group of memory cells corresponding to a first range of logical block addresses (LBAs). The operations performed by the processing device further include receiving a memory access command with respect to the group of memory cells. The operations performed by the processing device further include responsive to determining that a data structure associated with the group of memory cells references a second range of LBAs, blocking the memory access command; responsive to determining that the first range of LBAs does not include each LBA of the second range of LBAs, performing, on the group of memory cells, a trim operation; and responsive to determining that the data structure indicates the completion of the trim operation, performing a memory access operation specified by the memory access command.

Managing trim commands in a memory sub-system

Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.

Address translation based on page identifier and queue identifier

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include receiving, by the processing device, a trim command on the memory device, wherein the trim command references a range of logical block addresses (LBAs). The operations performed by the processing device further include identifying a group of memory cells corresponding to the range of LBAs, wherein the group of memory cells comprises one or more management units (MUs). The operations performed by the processing device further include updating a data structure associated with the group of memory cells to reference the request; receiving a memory access command with respect to the group of memory cells. The operations performed by the processing device further include responsive to determining that the data structure associated with the group of memory cells references the trim command, blocking the memory access command; performing, on the group of memory cells, a trim operation specified by the trim command; updating the data structure to indicate the completion of the trim operation; and responsive to determining that the data structure indicates the completion of the trim operation, performing a memory access operation specified by the memory access command.

A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.

Interruption of program operations at a memory sub-system

A method includes receiving signaling indicative of performance of a reset operation involving a first physical function associated with a controller of a memory device and initiating a first timer that corresponds to an amount of time available for the first physical function associated with the controller of the memory device to complete execution of pending commands. The method further includes initiating a second timer that corresponds to an amount of time available for a second physical function associated with the controller of the memory device to complete execution of pending commands and initiating a third timer that corresponds to an amount of time available for the second physical function associated with the controller of the memory device to join a recovery operation that is instigated as a result of performance of the reset operation.

Seamless recovery of a hardware-based I/O path in a multi-function NVMe SSD

A processing device in a memory sub-system receives a plurality of requests to perform a plurality of input/output (IO) operations corresponding to a plurality of logical devices associated with a memory device and assigns the plurality of requests to respective queues associated with the plurality of logic devices. The processing device further iteratively processes the plurality of requests in view of respective numbers of operation credits associated with the plurality of logical devices, wherein the respective numbers of credits are based at least in part on respective sets of quality of service (QoS) parameters for the plurality of logical devices.

Quality of service control of logical devices for a memory sub-system

A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.

Cache operations in a hybrid dual in-line memory module

Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute the set of data access requests in a second order. The processing device can further identify a late data access request of the set of data access requests and determine whether a data structure in a local memory associated with the processing device includes a previous outstanding data access request corresponding to an address associated with the late data access request. Responsive to determining that the data structure includes an indication of a previous outstanding data access request corresponding to the address associated with the late data access request, identifying a type of data dependency associated with the previous outstanding data access request and performing one or more operations associated with the type of data dependency.

Managing data dependencies for out of order processing in a hybrid DIMM

A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

Managing collisions in a non-volatile memory system with a coherency checker

Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device operatively coupled to the first and second memory components. The processing device can perform operations including receiving a data access operation and, responsive to determining that a data structure includes an indication of an outstanding data transfer of data associated with a physical address of the data access operation, determining whether an operation to copy the data, associated with the physical address, from the first memory component to the second memory component is scheduled to be executed. The processing device can further perform operations including determining to delay a scheduling of an execution of the data access operation until the operation to copy the data is executed.

Managing data dependencies in a transfer pipeline of a hybrid dimm

An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.

Systems and methods are disclosed including a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device operatively coupled to the first and second memory devices can track access statistics of segments of data stored at the second memory device, the segments having a first granularity, and determine to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the segment of data from the first memory device and store the additional data at the second memory device to form a new segment having the second granularity.

Low latency cache for non-volatile memory in a hybrid DIMM

Growing community of inventors

Foster City, CA, United States of America

Horia Cristian Simionescu