Synopsys, Inc.

Horia A Toma

Namit Gupta

Mahantesh D Narwade

Jean-Marc Albert Forey

Srinivas Bongoni

Andrea Kroll

Thorsten Heiner Groetker

Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.

Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness

To perform a simulation, a design can be divided into 'blocks' described by models. To ensure that data is efficiently transferred from an source model to a destination model, a dynamic first-in first-out (FIFO) can be placed between these models. The initial size of the dynamic FIFO can be set to a relatively small value. To prevent deadlock, the size of the FIFO can be automatically increased in size by increments. In this manner, the memory resources of the FIFO can be tightly controlled. Advantageously, the size of the optimized dynamic FIFO can be used as the desired size of the FIFO implemented in silicon, thereby also ensuring efficient use of silicon resources.

Dynamic FIFO for simulation

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Sunnyvale, CA, United States of America

Horia A Toma