Intel Corporation

Amazon Technologies, Inc.

Horace Lau

Tony Lee Werner

Aravind Kalaiah

Vijay Korthikanti

Sundeep Amirineni

Dana Michelle Vantrease

Amir Khosrowshahi

Andrew Yang

Carey Kevin Kloss

Naveen Gandham Rao

Kiran Bachchu

Siddharth Malkani

A technique to stress test an integrated circuit design under test in a simulation environment may include running a simulation that includes providing bus interface transactions and idle cycles on a bus interface of an integrated circuit design. The technique may further include capturing bus interface activity on the bus interface during the simulation to generate a stimulus file and replaying the simulation by executing a test bench driver that reads the stimulus file and injects the bus interface transactions with modified idle cycles onto the bus interface of the integrated circuit design.

Testing integrated circuit designs with accelerated replay

Aggregation of coverage data for a design-under-test (DUT) can be performed using a coverage testbench without running any simulations on the DUT. Stimulus data that was used previously for performing different simulations on the DUT can be saved in a database. The coverage testbench can read the saved stimulus data and aggregate the coverage data from the stimulus data using a coverage model. When the DUT is updated, the coverage model can be updated, and updated coverage data can be collected using the coverage testbench without re-running the simulations on the DUT.

Offline functional coverage collection

In one embodiment, a matrix operation may be performed on one or more matrix operands. For example, matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands. The one or more matrix operands may be extracted from the matrix data. A matrix routine associated with the matrix operation may be identified. The matrix routine may be executed on a matrix processor using the one or more matrix operands. A result of the matrix operation may be obtained based on the matrix routine executed by the matrix processor.

Programmable matrix processing engine

An apparatus may comprise a multi-dimensional memory, a plurality of matrix processors, and a matrix routine memory. The matrix routine memory may store a plurality of programmable matrix routines, wherein each programmable matrix routine comprises a plurality of instructions associated with a particular matrix operation, wherein the plurality of instructions is to be executed by the plurality of matrix processors. Further, the plurality of matrix processors may be configured to: receive a command to perform a matrix operation; receive matrix data from the multi-dimensional memory; extract one or more matrix operands from the matrix data; identify a programmable matrix routine associated with the matrix operation; receive the programmable matrix routine from the matrix routine memory; execute the programmable matrix routine using the one or more matrix operands; and obtain a result of the matrix operation based on execution of the programmable matrix routine.

In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the max pooling operation using the one or more matrix operands; and obtain a result of the max pooling operation.

Max pooling in a matrix processing architecture

Described herein are one or more integrated circuits (ICs) comprising controller circuitry to receive a command to execute an operation for data inputs stored in an external memory or a local memory, and convert the operation into a set of matrix operations to operate on sub-portions of the data inputs. The IC(s) further comprise at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include ALUs, a local memory external to the ALUs and accessible by the ALUs, and processing control circuitry to create at least one matrix operand in the local memory (from the data inputs of the operation) comprising at least one of a scalar, a vector, or a 2D matrix, and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing a matrix operation.

Growing community of inventors

Mountain View, CA, United States of America

Horace Lau