Samsung Electronics Co., Ltd.

Hoon Lim

Soon-Moon Jung

Han-Byung Park

Won-seok Cho

Jae-Hun Jeong

Jong-Hyuk Kim

Kun-Ho Kwak

Hoo-Sung Cho

Gong-Heum Han

Bo-Tak Lim

Chang-Min Hong

Hyou-Youn Nam

Sung-Jin Kim

Won-Seok Cho

Jae-Joo Shim

Jae-hoon Jang

Byung-Jun Hwang

Sung-bong Kim

Cha-Dong Yeo

Youngho Lee

Hyungsoon Jang

Jae Hong Kwon

Eunguk Chung

Byoung-Keun Son

Jin-Ho Kim

Sung-jin Kim

Jae-Hoon Jang

Seung-jae Lee

Young-Chul Jang

Myang-Sik Han

Jung Min Lim

Sun-ha Hwang

Gyu-Ho Lyu

Joo-young Kim

Sang Hyup Lim

Soo-Seun Lee

A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

Semiconductor device and method of fabricating the same

Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.

Semiconductor device having silicide on gate sidewalls in isolation regions

Bottle for packaging

An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs.

Interconnection structure and electronic device employing the same

A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and fourth transistors may be arranged on first and second semiconductor layers formed over the first and second active regions. Fifth and sixth transistors may be arranged on the third and fourth semiconductor layers over the first and second semiconductor layers. A word line may be arranged in a straight line between the first and second gates of the first and second transistors and between the third and fourth gates of the third and fourth transistors.

Full CMOS SRAM

A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

Methods of forming semiconductor devices having self-aligned bodies

In a stacked load-less static random access memory (SRAM) device in which a pair of transmission transistors is stacked on a pair of driving transistors, the stacked load-less SRAM device includes first and second transistors arranged in first and second active regions separately on a semiconductor substrate and third and fourth transistors arranged on first and second semiconductor layers over the first and second transistors. A first drain region of the first transistor, a third drain region of the third transistor, and a second gate of the second transistor are electrically connected through a first contact node. A second drain region of the second transistor, a fourth drain region of the fourth transistor, and a first gate of the first transistor are electrically connected through a second contact node.

Stacked load-less static random access memory device

A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

Semiconductor memory device having three dimensional structure

Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers.

Semiconductor memory devices having vertically-stacked transistors therein

A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

Semiconductor device having a plurality of stacked transistors and method of fabricating the same

Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.

Semiconductor devices having thin film transistors and methods of fabricating the same

Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.

Semiconductor transistor with multi-level transistor structure and method of fabricating the same

Growing community of inventors

Seoul, South Korea

Hoon Lim