Micron Technology Incorporated

Nan Ya Technology Corporation

Micro Technology, Inc.

Hoon Choi

Qiang Tang

Ali Feiz Zarrin Ghalam

Eric N Lee

Jongtae Kwak

Seong-Hoon Lee

Daesik Song

Onegyun Na

Ramin Ghodsi

Luigi Pilolli

Agatino Massimo Maccarrone

Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal

Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.

Apparatus and methods for serializing data output

Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Current sense amplifiers, memory devices and methods

In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal

Apparatuses and methods for charge sharing, between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit. The charge sharing circuit may be coupled to the first line and the second line and configured to receive a first data signal and a second data signal. The charge sharing circuit may be further configured to cause charge to be shared between the first line and the second line responsive, at least in part, to the first data signal and the second data signal having different logic levels.

Apparatuses and methods for line charge sharing

A system includes a plurality of sensing devices, a first multiplexer, a plurality of local return clock signal paths, a second multiplexer, and a data latch. Each sensing device outputs data onto a respective local data path in response to a clock signal on a clock signal path. The first multiplexor passes data from a selected local data path to a global data path. Each local return clock signal path is coupled to the clock signal path at a respective sensing device such that each local return clock signal path is routed along with a respective local data path. The second multiplexor passes a return clock signal from a selected local return clock signal path corresponding to the selected local data path to a global return clock signal path. The data latch latches the data on the global data path into the data latch in response to the return clock signal on the global return clock signal path.

Data path with clock-data tracking

The invention provides the power generator includes a bias voltage generator and a voltage clamping circuit. The bias voltage generator receives a reference voltage and generates a bias voltage according to the reference voltage. The voltage clamping circuit is coupled to the bias voltage generator. The voltage clamping circuit receives a supply voltage and the bias voltage and respectively outputs a plurality of data line power to the data transporting buffers by clamping the supply voltage according to the bias voltage. Wherein, the supply voltage is varied between a voltage range, and voltage levels of the data line powers are all constant.

Power generator for data line of memory apparatus

Apparatuses and methods for charge sharing between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit. The charge sharing circuit may be coupled to the first line and the second line and configured to receive a first data signal and a second data signal. The charge sharing circuit may be further configured to cause charge to be shared between the first line and the second line responsive, at least in part, to the first data signal and the second data signal having different logic levels.

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Boise, ID, United States of America

Hoon Choi