Apple Inc.

Sun Microsystems, Inc.

P.a. Semi, Inc.

Honkai Tam

Jim Chen Chou

Daniel C Murray

Arthur L Spence

John H Mylius

Roy Gideon Moss

Pradeep Kanapathipillai

Peter J Bannon

Andrew J Beaumont-Smith

Pradeep R Trivedi

Edgardo F Klass

Greg M Hess

Shih-Chieh Wen

Bo Tang

Yun Gong

Sribalan Santhanam

Rajat Goel

Andrew J Demas

Pranjal Srivastava

Jung-Cheng Yeh

Sanjay P Zambare

An electronic device includes a display panel and image processing circuitry. The image processing circuitry receives input image data corresponding to an image to display on the display panel, modifies the input image data by executing a first context task (e.g., lower priority task), and receives a context switch request. The image processing circuitry also pauses modification of the input image data by pausing execution of the first context task and then switches to modifying the input image data by executing a second context task (e.g., higher priority task).

Low-latency context switch systems and methods

An electronic device may include angle detection circuitry to receive input image data including a channel of pixel data and determine pixel statistics based on a difference between a first pixel cluster and a second pixel cluster, and the second pixel cluster is offset from the first pixel cluster at a first angle. The pixel statistics may also be based on a difference between the first pixel cluster and a third pixel cluster, wherein the third pixel cluster is offset from the first pixel cluster a second angle, different from the first angle. The angle detection circuitry may also determine a best angle based on the differences, wherein the best angle approximates an angle of uniformity in content of the image. Image processing circuitry may then modify the input image data based on the best angle by modifying pixel values of the channel of pixel data.

Angular detection using sum of absolute difference statistics systems and methods

In one embodiment, a rotator, a mask generator, and circuitry configured to mask the rotated operand output by the rotator with the output mask generated by the mask generator perform a shift operation. The rotator is configured to rotate the input operand by the shift count. The mask generator is configured to generate an output mask by decoding a most significant bit (MSB) field of the shift count to generate a first mask, decoding a least significant bit (LSB) field of the shift count to generate a second mask, logically ANDing the bits of the second mask with the corresponding bit of the first mask and logically ORing the result with an adjacent bit of the first mask that is selected responsive to the shift direction.

Fast static rotator/shifter with non two's complemented decode and fast mask generation

A scannable latch circuit is disclosed. In one embodiment, the scannable latch circuit includes a master latch, a slave latch, and a gating circuit coupled between the master latch and the slave latch. The slave latch may be implemented to support scan-shifting for test operations. Scan data received by the master latch may be provided to the slave latch through the gating circuit. The gating circuit may enable data to be transferred from the master latch to the slave latch when a scan enable signal is asserted. When the scan enable signal is deasserted, the gating circuit may cause the slave latch to output a constant (i.e. unchanging) state, regardless of the state of data stored in the master latch. This may result in power savings by inhibiting the slave latch from making state changes when scan-shifting operations are not in progress.

Low power scannable latch

In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies

A flop circuit comprises a precharge circuit for precharging a first node in response to an occurrence of a first phase of a timing signal, and a discharge circuit for conditionally discharging the first node in response to an occurrence of a second phase of the timing signal depending upon a data input signal. The flop circuit further comprises a voltage retention circuit, such as a latch, configured to store a retained logic value that depends upon a logic value present at the first node during at least a portion of the second phase of the timing signal, and an output circuit configured to generate an output signal that depends upon the data input signal. The output circuit may be configured to drive the output signal in a first logic state when the first node is discharged regardless of the retained logic value, and may be configured to drive the output signal in a logic state that depends upon the retained logic value when the first node is charged. In one particular embodiment, the output circuit is implemented using a NAND gate.

Low latency flop circuit

In one embodiment, a state determiner comprises a plurality of logic circuits and a second logic circuit. Each logic circuit corresponds to a respective bit position of a result of an adder. A first logic circuit corresponds to a least significant bit of the result and is coupled to receive a least significant bit of each operand of the adder and a carry-in input to the adder. Each remaining logic circuit is coupled to receive a bit from the respective bit position of each operand and a less significant bit adjacent to the bit of each operand. Each logic circuit generates an output signal indicative of whether or not a specific result occurs in the respective bit position of the result. Coupled to receive the output signals second logic circuit is configured to generate a sum signal indicative, when asserted, that the specific result occurs.

Fast modular zero sum and ones sum determination

Selection circuitry for use in register files, multiplexers, and so forth is disclosed. The selection circuitry includes a plurality of local bit lines coupled to global bit line circuitry. Groups of cells or data inputs are coupled to each of the local bit lines. When a cell or data input of a given group is selected, a group select signal is provided to the global bit line circuitry. The global bit line circuitry drives a global bit line responsive to the group select signal and the data driven on (or provided to) the local bit line associated with the selected cell/input, thus providing a data output. When no cell of a given group is selected, the group select signal is de-asserted, causing the respective global bit line to be held in a predetermined state.

Keeperless fully complementary static selection circuit

A memory circuit may include a pair of cross-coupled inverters configured to store a bit of data and a first transistor coupled to a first node of the pair of cross-coupled inverters. A plurality of transistors that form the pair of inverters have a first nominal threshold voltage. The first transistor is coupled to a first bit line, and has a second nominal threshold voltage that is lower than the first nominal threshold voltage. The first transistor may be a write transistor and another write transistor having the second nominal threshold voltage is coupled to the other node of the pair of cross-coupled inverters. A register file may include a bit storage section that includes at least one pair of the cross-coupled inverters; a write transistor section and a read transistor section having the second nominal threshold voltage.

Multiple threshold voltage register file cell

In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

Combined multiplex or/flop

A system and method of resetting a jam latch circuit includes an activation device. The activation device having respective inputs coupled to each one of several data lines. A first reset device is also included and has a first control input coupled to an output of the activation device. The first reset device having a reset voltage source coupled to an input of the first reset device. A second reset device is also included and has a second control input coupled a control signal. The second reset device being coupled in series with the first reset device. A storage cell is coupled to an output of the second reset device.

System and method for providing a fast and power efficient jam latch

A carry look-ahead adder capable of adding or subtracting two input signals includes first stage logic having a plurality of carry-create and carry-transmit logic circuits each coupled to receive one or more bits of each input signal. Each carry-create circuit generates a novel carry-create signal in response to corresponding first bit-pairings of the input signals, and each carry-transmit circuit generates a novel carry-transmit signal in response to corresponding second bit-pairings of the input signals. The carry-create and carry-transmit signals are combined in carry look-ahead logic to generate accumulated carry-create signals, which are then used to select final sum bits.

Growing community of inventors

Redwood City, CA, United States of America

Honkai Tam