Marvell International Limited

Maxlinear, Inc.

China Petroleum Chemical Corporation

Shanghai Research Institute of Petrochemical Technology, Sinopec

Chiplego Technology (shanghai) Co., Ltd.

Hongyu Zhang

Weimin Yang

Bin Zhang

Shoumeng Yan

Bin Yang

Wei Jun Zheng

Hongmin Sun

Yong Yao

Mingyao Huan

Zhenhao Shen

Wenjie Liu

Guobin Zhang

Yichen Liu

Yanwei Ji

Sheau Jiung Lee

A bus pipeline structure comprises: an n-channel multiplexer at a transmitting end works in an n times of clock domain of a transmitting chiplet; the n-channel multiplexer sends a data flow from the transmitting chiplet to an n-channel de-multiplexer at a receiving end, the n-channel de-multiplexer inputs the received data flow into a first register in an idle state among at least two registers at the receiving end, the first register outputs the received data flow to a receiving chiplet; after a receiving state machine at the receiving end determines that the n-channel de-multiplexer sends the received data flow to the first register, the receiving state machine at the receiving end sends a bus release flag to a transmitting state machine at the transmitting end, and the transmitting state machine receiving the bus release flag controls an n-channel multiplexer to transmit the data flow in a next clock cycle.

Bus pipeline structure for die-to-die interconnect and chip

A method for scheduling a computational task is proposed. The method includes receiving, at a server, a request for executing a computational task from a client device. The method further includes forwarding the computational task to a processing device if a predetermined condition is fulfilled. The predetermined condition can be based on an execution time or on a security level of data of the computational task, for example.

Method for scheduling a computational task, a method for processing a computational task, a computer readable storage medium, a computer program, a residential gateway, and a server

System and methods are provided for processing composite video signals. The system includes: a clock synthesizer configured to generate a line lock clock signal; an interpolation unit configured to generate source data associated with a source composite video signal, the source composite video signal being related to a source clock signal; a buffer unit configured to store the source data based at least in part on the source clock signal and provide destination data based at least in part on the line lock clock signal; a signal processing unit configured to process the destination data to extract a synchronization component and determine a phase error between the synchronization component and the line lock clock signal. The clock synthesizer is further configured to adjust the line lock clock signal based at least in part on the phase error.

Systems and methods for processing composite video signals

Processes for catalytically synthesizing ethylbenzene from ethanol and benzene comprising:

Processes for synthesizing ethylbenzene from ethanol and benzene

Growing community of inventors

Shanghai, China

Hongyu Zhang