Marvell International Limited

Marvellworld Trade Ltd.

Marvell Asia Pte., Ltd.

Hongying Sheng

Vivek Raghunath Khanzode

Roger Longstreet

Pantas Sutardja

Gregory Burd

Zining Wu

Chen Liu

Wei Cao

Toai Doan

Lei Wu

Job Lam

Kai-Chuan Chang

Jianke Li

Vasudev V Pai

Panu Chaichanavong

Nitin Nangare

Supaket Katchmart

Vincent M Wong

Henri Sutioso

Naim Siemsen-Schumann

Jun Wang

Sameer Vaidya

Vivek Khanzode

Pallavi Joshi

A storage device controller includes drive controller circuitry configured to control writing and fetching of data from a storage medium, read data channel circuitry for interfacing between the drive controller circuitry and the storage medium, test controller circuitry configured to test the read data channel circuitry by issuing test commands simulating the writing and fetching of data from the storage medium, and selector circuitry configured to switchably couple the read data channel circuitry to the drive controller circuitry in an operating mode and to the test controller circuitry in a testing mode. The storage device controller may include a pattern generator configured to output the test commands. Processor circuitry may be configured to store test results in memory, to compute performance metrics from the stored test results, and communicate the performance metrics to a host device.

United states test controller for system-on-chip validation

Systems and methods of reading data from a storage device are provided. A first codeword and a second codeword are read from a storage device, where the second codeword is positioned after the first codeword. The first and second codewords are decoded in parallel, and the decoding of the second codeword completes before the decoding of the first codeword completes. The decoded second codeword and a signal indicating whether the decoding of the second codeword is complete are transmitted to control circuitry before the decoding of the first codeword completes.

Systems and methods for reading and decoding encoded data from a storage device

A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.

System on a chip serial communication interface method and apparatus

An integrated circuit including a first decoder, a second decoder, a sensor, and a controller. The first decoder generates first data by performing a first number of decoding iterations and generates second data after performing all of the first number of decoding iterations. The second decoder performs a second number of decoding iterations and generates soft information based on input samples and/or the second data. Each of the second number of decoding iterations is performed after all of the first number of decoding iterations. The first decoder generates the first data based on the soft information and/or the first data from one of the first number of decoding iterations. The sensor senses a temperature of the integrated circuit. The controller controls, based on the temperature of the integrated circuit, at least one of the first number of decoding iterations or the second number of decoding iterations.

Method and apparatus for controlling a number of decoding iterations of a decoder based on a temperature of an integrated circuit that includes the decoder

Apparatus having corresponding methods and storage devices comprise: an iterative decoder configured to generate codewords based on input samples, wherein the iterative decoder is further configured to perform a number of decoding iterations for each codeword, wherein the number of decoding iterations is an integer greater than zero, and wherein the number of decoding iterations does not exceed a limit number; and a sensor configured to generate one or more measurements of a physical variable, wherein the limit number is set in accordance with the one or more measurements generated by the sensor.

Controlling decoder iterations based on measurements of physical variables

A data storage device includes a storage medium on which data is stored in overlapping tracks, and a medium controller that directs storage of data on, and reading of data from, the storage medium, including encoding data being stored and decoding data being read. The decoding includes, when reading a first track, cancelling interference from a second track that overlaps the first track. The data storage device also includes a host controller in communication with the medium controller. The host controller includes memory that stores data decoded, and data to be written, by the medium controller. Communication between the medium controller and the host controller includes signals derived from data on said first and second tracks for facilitating the cancelling. A method of operating a data storage device includes, when reading a first track, facilitating the cancelling by communicating signals derived from the data on the first and second tracks.

Storage device interface for shingled magnetic recording system

Embodiments of the present disclosure provide for reading data from a physical storage medium, transferring the data between a data channel and a test interface over a parallel data bus, and providing the data from the test interface at a serial port in a serial format.

Method and apparatus for communicating with a disk controller for testing

A filter network having a variable cut-off frequency can be controlled in a way that allows the cut-off frequency to be changed gradually to avoid undesirable transient effects. An impedance network (such as a resistor network) that provides a plurality of impedance values is provided. Logic, and a corresponding method, are provided to change the impedance value gradually, such as on a step-wise basis, to change the cut-off frequency gradually. The size of the impedance step and the duration of the step can be preprogrammed, and may be different for different types of events that trigger the need for a frequency change. It may also be possible for those preprogrammed values to be initial values only, with the values changing under programmed control during the frequency changing process. Other values, such as the initial and target impedance values that determine the initial and target frequency, also may be programmable.

Filter with controlled cut-off frequency step-down

A system including a first clock module, a second clock module and an adjustment module. The first clock module is configured to generate a first clock signal having a first frequency. The second clock module is configured to, based on the first clock signal, generate a second clock signal for an integrated circuit. An amount of current drawn by the integrated circuit is based on a second frequency of the second clock signal. An adjustment module is configured to receive an enable signal indicating whether the integrated circuit is being powered ON. In response to the enable signal indicating the integrated circuit is being powered ON, the adjustment module (i) determines a predetermined frequency, and (ii) generate a control signal based on the first clock signal. The control signal adjusts the second frequency of the second clock signal to be between the predetermined frequency and the first frequency.

System and method of adjusting current drawn by an integrated circuit based on frequencies of clock signals

Some of the embodiments of the present disclosure provide a method comprising receiving a stream of codewords from a hard disk controller (HDC), receiving a write gate signal, the write gate signal configured to request a read/write (R/W) channel to write at least a first part of the stream of codewords to a media, and receiving a symbol count signal indicating a number of symbols in the first part of the received stream of codewords. Other embodiments are also described and claimed.

Long latency protocol for hard disk controller interface

A control system includes a clock gating module and a clock comparison module. The clock gating module is configured to generate a gating signal based on an enable signal, a given period, and a base clock signal having a given frequency. The clock comparison module is configured to generate a gated clock signal based on the base clock signal and the gating signal.

Systems and methods for controlling power supply current using clock gating

A read-channel module including a VGA module to amplify a signal based on a variable gain, an ADC module to generate a sample based on the amplified signal, and an AGC module to control the variable gain of the VGA module. A gain adjusting module generates (i) a first gain and (ii) a second gain when an amplitude of the sample is (i) less than or equal to a first predetermined threshold and (ii) greater than or equal to a second predetermined threshold, respectively. The AGC module (i) increases and (ii) decreases the variable gain of the VGA module based on (i) the first gain and (ii) the second gain, respectively. The gain adjusting module generates the first gain and the second gain by (i) multiplying a present gain of the AGC module by a predetermined multiplier or (ii) adding a predetermined offset to the present gain.

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San Jose, CA, United States of America

Hongying Sheng