United Microelectronics Corp.

Winbond Electronics Corporation

Hongyi Chen

Qingming Shu

Yongming Li

Xiaodong Wu

Xiaohai Qiu

Zhiqiang Zeng

Weixin Gai

A method for performing a motion estimation combined with a Walsh-Hadamard transform algorithm. In image frame, which includes a pixel array to display an image object, the method includes fetching a current image pixel content C and a reference image pixel content R. A Walsh-Hadamard transform algorithm is used to transform the current image pixel content C and the reference image pixel content R, so that a WHT SAD(i, j), WSAD(i,j) is computed to serve as a matching criterion. The formula for computing WSAD(i,j) is ()=()=(())=, where E is the difference macro block (MB) of a current MB and a reference MB, (x, y) is the location of current MB, (i,j) is the candidate motion vector, i.e., the location of reference MB, N is the MB size, and t=t&#xb7;t', where tis a matrix by a product of two basis tand Trans[t].

Method for performing motion estimation with Walsh-Hadamard transform (WHT)

The invention provides a method for a motion estimation algorithm. The motion estimation algorithm using low bit resolution integrated edge image instead of luminance image to obtain difference block with small AC coefficients, edge image created by filters is employed to improve encoding quality, on the other hand, operation cost is reduced to low bit resolution. The invention also provides a method for a motion estimation algorithm with a new algorithm using low-bit resolution oriented edge image. Using low-bit resolution oriented edge in motion estimation can result in flatter image blocks which is in demanded by texture-compress unit (such as DCT), as a result, the encoding efficiency is improved, and the operation load is reduced by low-bit resolution.

Method for motion estimation using a low-bit edge image

An apparatus and a method of fast rotation. A pipeline comprising a plurality of multiplexes a plurality of shifters to perform last rotation of data selected by the multiplexes, and a plurality of adders/subtracters is provided. A plurality sets of data is input to be filtered and selected by the multiplexes. Fast rotation is performed to the data selected by the multiplexes. A final computation is performed a set of resultant data is output through the adder/subtractors.

Method and apparatus for fast rotation

A VLSI wavelet transform (WT) architecture suitable for use in a discrete wavelet transform (DWT) or a discrete wavelet packet transform (DWPT). The WT architecture has a multiplier; an accumulator; at least two address generators that has a first address generator and a second address generator; a control unit; a memory of result that stores computation results; and a memory of table, which pre-stores all possible weights, each of which weights is a product of some specified filter coefficients for performing a DWT/DWPT with parameters of decomposition level, length of data segment, and filter length. The first address generator and the control unit receive data input, the control unit exports control signals to multiplier, accumulator, second address generator, and memory of table. The memory of the table also receives outputs from the first address generator and the second address generator to select the desired weights of the filter coefficients, which are sent to the multiplier to obtain a product with the data input. The product is sent to the accumulator to add into a corresponding sum, and the memory of result receives the corresponding sum and an address output of the second address generator to address the received corresponding sum, in which when all of the data input in the DWT/DWPT are completely inputted, each the corresponding sum is an end result of the DWT/DWPT.

Architecture of discrete wavelet transformation

A method and an apparatus for controlling calculation error produced by the accumulation error due to digit truncation in a non-integer computation. The error is eliminated by controlling the values of LSB, C.sub.in and the addition/subtraction selecting signal as, so that C.sub.in is not necessarily equal to C.sub.in. Considering a even number of cascaded pipelines, C.sub.in in the odd pipelines is set as 0, wherein C.sub.in in the even pipelines is set as 1. The resultant error is thus eliminated mutually by odd and even pipelines.

Method and apparatus for controlling calculation error

A method of signal compression. An input signal is divided into a plurality of segments. Each of the segments is decomposed by wavelet packet transform to a plurality of levels, so that each of the segments is in a form of a group of coefficients in each of a plurality of domains corresponding to each of the levels. Each of the domains is divided into a plurality of sub-domains to calculate a degree of characteristic concentration corresponding thereto. One of the domains having a highest degree of characteristic concentration is select to perform bit allocation and quantization, so that the group of coefficients in the selected domain is represented as an information. The information is formatted into a frame for transmission, and then the frame is output.

Method of signal compression

A systolic linear-array modular multiplier is provided, which can perform the modular multiplication algorithm of P. L. Montgomery more efficiently. The total execution time for n-bit modular multiplication is 2n+11 cycles. The modular multiplier includes a linear array of processing elements which is constructed based on a pipeline architecture that can reduce the computation procedure by one clock period. Each of the processing elements is simple in structure, which is composed of four full adders and fourteen flip-flops. For n-bit modular multiplication, a total number of 46n+184 gates is required, which is substantially less as compared to the prior art, so that manufacturing cost of the modular multiplier can be significantly reduced. These features make the modular multiplier suitable for use in VLSI implementation of modular exponentiation which is the kernel computation in many public-key cryptosystems, such as the RSA (Rivest-Shamir-Adleman) system. With the 0.8 .mu.m CMOS technology, a clock signal up to 180 MHz can be used. In average, for n-bit modular multiplication, the encryption speed can reach 116 Kbit/s (kilobits per second), which is substantially twice that achieved by the prior art.

Systolic linear-array modular multiplier with pipeline processing

A current-mode four-quadrant analog multiplier is provided, which is constructed based on CMOS (complementary metal-oxide semiconductor) technology, capable of generating an output current signal which is proportional in magnitude to the product of two input current signals. This current-mode analog multiplier is designed based on the translinear circuit principle. The current-mode analog multiplier has high precision, wide current dynamic range, and is insensitive to temperature and process, suitable for use in VLSI implementation of many analog circuits and systems, such as fuzzy logic controllers and analog neural networks.

CMOS current-mode four-quadrant analog multiplier

An adaptive block-matching motion estimator for used in a video coding system wherein the adaptive block-matching motion estimator is less in hardware complexity and latency time and is therefore more cost-effective to implement and higher in performance. This adaptive block-matching motion estimator includes a DS array for processing the pixel data of the current image block and the pixel data of the compared image block to thereby obtain a difference vector and a set of weight bits; a compression array having a first output port for outputting a compressed sum vector and a second output port for outputting an associated compressed carry vector, with the difference vector and the set of weight bits from the DS array along with the compressed sum vector and the associated compressed carry vector being taken as the inputs to the compression array; and a complexity-matching (CM) unit for processing the compressed sum vector and the associated compressed carry vector from the compression array to thereby produce the desired motion vector.

Adaptive block-matching motion estimator with a compression array for

A process for obtaining a motion vector for motion estimation used in a video image analysis, utilizing a block matching algorithm, which has the effect of reducing the computational load that is placed on the hardware logic used for implementation of the process. In a process of obtaining the absolute error value for the compared image block, a preliminary comparison is performed for every processed pixel in the image block to determine if the set minimum value of the absolute error function represented by a motionless tolerance constant is achieved. It is not necessary to obtain every actual value of the absolute error function. The block matching scheme of providing motion estimation enables hardware implementing the process to discontinue processing if the desired motion vector is selected prior to all image blocks being compared.

Motion estimation block matching process and apparatus for video image

An apparatus for implementing motion estimation block matching for video image processing. The apparatus receives pixel data of original and compared image blocks for comparison, to obtain an image motion vector. The apparatus has a multi-stage pipelined tree-architecture that includes a computation stage, a summation section, an accumulation stage, and a minimum value evaluation stage. The computation stage includes 2.sup.n computation members for producing a difference error value and a sign bit of the compared image blocks. The summation section coupled at the pipelined stage next to the computation stage, includes a series of summation stages for producing an absolute error value of the compared image blocks. A following accumulation stage adds an output of the single adder means of the last summation stage and a last un-added sign bit, for producing a sum. A last minimum value evaluator evaluates and generates the minimum of the output of the accumulation stage, as the motion vector for the implementation of motion estimation block matching for video image processing. Only a single adder is required in each of the computation members to reduce both the complexity and the processing delay for increased performance.

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Beijing, China

Hongyi Chen