Nxp Usa, Inc.

Nxp B.v.

Hongyan Yao

Jie Jin

Yizhong Zhang

Stefano Pietri

Michael Todd Berens

Yang Wang

Yikun Mo

Jiawei Fu

Yan Huang

Jianluo Chen

Sitong Wang

Linhao Cao

A self-calibrated buffered-voltage DAC includes a DAC configured to receive an input digital signal and output a first analog voltage signal, a buffer amplifier configured to receive the first voltage signal from the DAC and provide a buffered second analog voltage signal, a voltage to frequency converter configured to selectively receive the first and second voltage signals and provide first and second output signals at respective first and second frequencies, a counter configured to receive the output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies, a comparator configured to receive the first and second digital output signals and provide a digital calibration offset, and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.

Self-calibrating buffered-voltage DAC

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fbased on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fwith a high frequency clock having a constant frequency f. A memory is included to store at least two counter values generating by comparing fand fonce when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

Self calibrating digital-to-analog converter

A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.

Glitch-free clock generator and method for generating glitch-free clock signal

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Suzhou, China

Hongyan Yao